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Old 2nd May 2007, 07:10 PM   #1
SandroN is offline SandroN  Brazil
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Question Question about DIR1703

Hi,
I have built a DAC with DIR1703 and AD1864 to play 44.1kHz 16bit CDs
My plan was to use the Current output mode for AD1864 into a I-V tube converter.
The problem: At Iout from AD1864, both channels looks very saturated.

Below, the scheme.
- load for Iout = 100 ohms
- all inverters 74HC04 at 3.3V
- R feedback for first SPDIF inverter = 22K ohms

Could someone point where is the error?
Could some of my ICs be damaged?
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Old 2nd May 2007, 07:41 PM   #2
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You are sending 16-bit right justified data to a device expecting 18-bit right justified data. Delay LRCK by 2 BCK cycles.
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Old 2nd May 2007, 09:10 PM   #3
SandroN is offline SandroN  Brazil
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Thanks a lot!!!!!
Yes. Shure it is the problem!

Is the delay circuit that one used in Audionote DAC 1.1 ? If not, do you suggest some scheme for delay circuit?

What pins in DIR1703 are equivalent to CS8412 FSYNC, SDATA and SCLK ?

I have IC 74AC02 on hand. Can I use it at 3.3V to make the delay circuit or do I have to use the 74HC02 ? Should I use 3.3V or 5.0V ?

Thanks again
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Old 2nd May 2007, 09:35 PM   #4
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The Audionote circuit does not apply here. In that circuit the data from the CS8412 is 18-bit right justified data. The DIR1703 does not have that option, so 'AC02's alone will not be much use. You will need flip-flops.
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Old 2nd May 2007, 11:07 PM   #5
SandroN is offline SandroN  Brazil
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Somebody has the scheme of the flip-flop circuit?
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Old 3rd May 2007, 12:24 AM   #6
SandroN is offline SandroN  Brazil
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hum...
looking at DIR1703 and AD1864 datasheets, I'm in doubt if "delay LRCK by 2 BCK cycles" will work.

From AD1864 datasheet:
- The last 18 bits sent to DAC will be converted to output when LL or LR goes to "0".

From DIR1703 datasheet:
- From graphs at pag. 13 and 15, it looks each LRCKO cycle (L+R data) has a fixed 64 BCKO. So, in theory, each channel has a "space" for 32 bit data.

So, AD1864 receive last 18 bit when LL/LR goes to "0".
If I have configured DIR1703 for 16-bit MSB first, right justified, AD1864 is receiving an undefined value for 1st and 2nd MSB for his 18-bit internal register.

I dont know if playing only 16bit Cds, I can put DIR1703 to output 24-bit MSB first, right justified.
Nor, if it works, I dont know if DIR1703 would convert 16bit data to 24bit correctly
ex: 1111111111111111 (16-bit) to
00000000111111111111111111 (24-bit)
or if the 8 MSB from 24bit word would still be undefined
ex: xxxxxxxx1111111111111111

Help!
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Old 3rd May 2007, 12:32 AM   #7
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Quote:
Originally posted by SandroN
hum...
looking at DIR1703 and AD1864 datasheets, I'm in doubt if "delay LRCK by 2 BCK cycles" will work.
Thats my cue to leave the stage.
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Old 3rd May 2007, 01:36 PM   #8
SandroN is offline SandroN  Brazil
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change DIR1703 output to 24bit didn't fix the problem. Sound changed to a high freq noise like white noise.
Change back to 16 bit
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Old 3rd May 2007, 03:57 PM   #9
rossl is offline rossl  United States
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The AD1864 datasheet is confusing.

The timing diagram at the bottom of page 7 shows left-justified data. Try setting the DIR1703 to 24-bit left justified.


edit: on second thought, it looks like the AD1864 is expecting 18 bits only and will not work with 16 or 24.
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Old 3rd May 2007, 04:33 PM   #10
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AD1864 require 18 bits right justified so 16 or 24 bits will not work definitely.
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