Hi all
I need your help.
I am studying the datasheet of CS8412. The following paragraph at page 23 makes me a bit confused particularly the last sentence.
"Format 11 is similar to format 0 except that SCK is an input and FSYNC is an output. In this mode FSYNC and SDATA are synchronized to the incoming SCK, and the number of SCK periods between FSYNC edges will vary since SCK is not synchronous to received data stream."
Provided that SPDIF input is 16 bits signal from a CD transport; CS8412 is fed with incoming SCK of 2.8224Mhz (44100 x 64) then CS8412 should output Fsync cycle equal to 64 SCK cycles (32 SCK cycle for each channel)? Since we have only 16 bits from CD so SDATA would content zeros from 17th to 32th SCK.
Is my understanding correct?
I need your help.
I am studying the datasheet of CS8412. The following paragraph at page 23 makes me a bit confused particularly the last sentence.
"Format 11 is similar to format 0 except that SCK is an input and FSYNC is an output. In this mode FSYNC and SDATA are synchronized to the incoming SCK, and the number of SCK periods between FSYNC edges will vary since SCK is not synchronous to received data stream."
Provided that SPDIF input is 16 bits signal from a CD transport; CS8412 is fed with incoming SCK of 2.8224Mhz (44100 x 64) then CS8412 should output Fsync cycle equal to 64 SCK cycles (32 SCK cycle for each channel)? Since we have only 16 bits from CD so SDATA would content zeros from 17th to 32th SCK.
Is my understanding correct?
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