Thank you dear. Nice project.
But as I understand, you can't have I2S and simultaneous mode at the same time...
You need to do your homework pet!
That's the whole point of the board - I2S in and what Iancanada calls PCM out with simultaneous latching of the + & - sdata. BCK is also stopped after the data has been latched in.
Here is the spec:
1. Support 16,18,20,24 bit PCM format output
2. Accept 16 to 32bit I2S input signals with SCK from 32*Fs to 64*Fs
3. Pure NOS mode with bit-perfect format converting
4. High speed design capable for 384KHz Fs with maximum MCLK up to 100MHz
5. Support PCM63,AD1865,AD1862,PCM1704,PCM1702,TDA1541/A and many other classical MULTIBIT DACs
6. Support TDA1541/A working at offset binary mode
7. Jumper selectable full-speed mode and half-speed mode
8. L,R simultaneous timing, launching D/A conversion at same latching edge to eliminate L/R phase difference
9. In order to reduce DAC noise floor, bit clock can be stopped after data shifted into DAC (default)
10. Delayed falling edge of latch enable signal (LLLR) applied to stop clock mode
11. Support dual mono DAC configuration
12. Jitter optimized synchronize logic architecture with last stage high speed low noise re-clocking flip-flops driven by original MCLK
nice to power a headphones amp....Anyway, look what Santa brought today...a 2,5KVA Balanced Power Transformer.
I can't wait for a new board from you which will be integrating usb with TDA1541A in simultaneous mode. It will probably also have some kind of reclocking with an oscillator next to TDA chip?
I'm sure it will be top-noch, so count me in - we can start an interest list.
Best Regards, Sl1
What surprises me every time I see this generic I2S input with diodes is that the TDA1543 has exactly this topology inside the chip, supplemented with diodes to earth and plus 5V.
Maybe someone can elaborate why this doubling is needed? For the TDA1541, yes, I can see the need to take this further development in the TDA1543 (and dittoA) as a new way of interfacing.
If we are talking about using diodes as a voltage reference as part of a divider for attenuation on the I2S, my reference is Thorsten Loesch designer at AMR via web diyhifi.org - but that 'its the same as the input stage of the chip and - how the f*ck did this come ever come about as a solution for attenuation?. ...'
Audial do not use I2S attenuation at all... But they do use sim-data mode but no FIFO and they do produce what is about as good as a 1541A DAC you will find. AMR does use I2S attenuation but does not use sim data mode, but does use FIFO.
And after all of these years you probably know this already = short answer if you want sim data and FIFO = build it your self. Only way. If you want 1541A PCB platform, buy from Pedja at Audial = the only worthwhile way, other wise just a hack, and including guys who sell oscillating designs (sorry - but its a fact).. oh yeah just change a resistor or two = not the point. How did it go to production like that in the first place = what else is compromised?.. best guess is quite a bit.
As always proven design works best, would be good if John could finalise a 1541A = agree.. but how and when?
LH/S
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Hi,
I know Pedja makes good stuff - I've had his Aya1 DAC for 10+ years. John also makes good stuff and even shares most of his knowledge with the public. For thanks people say he changes his mind too often when he comes to a realisation and makes a turn - well, it's called development.
Look - a lot of people work on developing the best DAC possible and some copying of ideas and solutions, some reinventing of old stuff somebody published in 1980s and so on comes with it.
And since this is supposed to be DIY for enthusiasts where we share and work together, I don't see a problem as long as we all recognise who came up with what. We all need some recognition for our work.
But I do see 2 problems:
- some people linger around until they gather enough info to build something and then they release "their" product and try to make money using other peoples ideas (basically that is the core of modern capitalism - take advantage of others to make money)
- some leading developers come up with designs using programmed controllers and chips which practically nobody can DIY at home and most people can't afford. For me, this is not DIY anymore. This is: buy it, connect it to a transformer and put it in a box. No velding, no understanding how it actually works, no fun.
I will certainly try to build my own FIFO when I learn enough about using shift registers and counters.
I know Pedja makes good stuff - I've had his Aya1 DAC for 10+ years. John also makes good stuff and even shares most of his knowledge with the public. For thanks people say he changes his mind too often when he comes to a realisation and makes a turn - well, it's called development.
Look - a lot of people work on developing the best DAC possible and some copying of ideas and solutions, some reinventing of old stuff somebody published in 1980s and so on comes with it.
And since this is supposed to be DIY for enthusiasts where we share and work together, I don't see a problem as long as we all recognise who came up with what. We all need some recognition for our work.
But I do see 2 problems:
- some people linger around until they gather enough info to build something and then they release "their" product and try to make money using other peoples ideas (basically that is the core of modern capitalism - take advantage of others to make money)
- some leading developers come up with designs using programmed controllers and chips which practically nobody can DIY at home and most people can't afford. For me, this is not DIY anymore. This is: buy it, connect it to a transformer and put it in a box. No velding, no understanding how it actually works, no fun.
I will certainly try to build my own FIFO when I learn enough about using shift registers and counters.
Coming here to post a question about the ecdesigns DEM clock and I2S attenuator back in post #2748!
Reminds me just how much of this thread I am yet to read, let alone absorb! Keep up the good work all of you.
I now feel like my question will relate to well outdated versions of implementation but it is where I am at.
Question:
The BCK signal that goes towards the DEM reclock should be without attenuation. Correct?
Without first being aware of the beautiful mosaic DAC of ecdesigns I have been drawing a modular dac in Eagle - it has ended up modular to fit in with the limitations of board size of free version of EagleCAD; I think it breaks down the gnd planes nicely; and I am enamoured by the Cambridge Audio 4 X parallel implementation that has multiple dac modules standing vertically to facilitate parallel operation.
Drawing the PCB in Eagle I have noticed that BCK is getting routed to the DEM recheck section after it has passed through the I2S attenuator. Should I redraw it so that the DEM recheck receives the "raw" BCK signal?
Thanks and good evening
Reminds me just how much of this thread I am yet to read, let alone absorb! Keep up the good work all of you.
I now feel like my question will relate to well outdated versions of implementation but it is where I am at.
Question:
The BCK signal that goes towards the DEM reclock should be without attenuation. Correct?
Without first being aware of the beautiful mosaic DAC of ecdesigns I have been drawing a modular dac in Eagle - it has ended up modular to fit in with the limitations of board size of free version of EagleCAD; I think it breaks down the gnd planes nicely; and I am enamoured by the Cambridge Audio 4 X parallel implementation that has multiple dac modules standing vertically to facilitate parallel operation.
Drawing the PCB in Eagle I have noticed that BCK is getting routed to the DEM recheck section after it has passed through the I2S attenuator. Should I redraw it so that the DEM recheck receives the "raw" BCK signal?
Thanks and good evening
Hi,
I know Pedja makes good stuff - I've had his Aya1 DAC for 10+ years. John also makes good stuff and even shares most of his knowledge with the public. For thanks people say he changes his mind too often when he comes to a realisation and makes a turn - well, it's called development.
Look - a lot of people work on developing the best DAC possible and some copying of ideas and solutions, some reinventing of old stuff somebody published in 1980s and so on comes with it.
And since this is supposed to be DIY for enthusiasts where we share and work together, I don't see a problem as long as we all recognise who came up with what. We all need some recognition for our work.
But I do see 2 problems:
- some people linger around until they gather enough info to build something and then they release "their" product and try to make money using other peoples ideas (basically that is the core of modern capitalism - take advantage of others to make money)
- some leading developers come up with designs using programmed controllers and chips which practically nobody can DIY at home and most people can't afford. For me, this is not DIY anymore. This is: buy it, connect it to a transformer and put it in a box. No velding, no understanding how it actually works, no fun.
I will certainly try to build my own FIFO when I learn enough about using shift registers and counters.
Agree about the capitalist thing - not something I'd support. But there is another option - you can easily buy Ian Canada's FIFO, isolator, reclock and PCM boards for not so much money and run it with your AYA.. then use Johns gifted DEM scheme (or not) and realise excellent sound without supporting any capitalist at all !!
LH/S
Thanks for the advice. I am aware of and curious about Ian's boards and already tried to get some used ones on this forum, but I was too late. New ones are too expensive for me - maybe at some other time of my life...
A little on-topic now:
As far as I know (maybe my info isn't the latest) BCK is best kept direct connection with nothing on it to preserve the signal intact as much as possible.
WS some people attenuate with diodes and say that is better than using resistors. I haven't compared it yet myself.
Data can be attenuated using resistors.
All this attenuation is because the TDA1541A chip reads 0s as voltage under 1.3V or so and 1s over 1.6V or so. So why feed it with 3 signals swinging from 0 to 5V at Mhz rates? It's better to attenuate this and give it a biased voltage, so that it swings up and down for 0.5V right in the region it is required by the chip. This decreases on-chip interference of the signals.
What chip does internally - if it has the same thing going on inside too - I don't know. But even if it does it internally, I guess it's better to do it externally anyway - lesser signals entering the chip mean less intermodulation regardless.
A little on-topic now:
As far as I know (maybe my info isn't the latest) BCK is best kept direct connection with nothing on it to preserve the signal intact as much as possible.
WS some people attenuate with diodes and say that is better than using resistors. I haven't compared it yet myself.
Data can be attenuated using resistors.
All this attenuation is because the TDA1541A chip reads 0s as voltage under 1.3V or so and 1s over 1.6V or so. So why feed it with 3 signals swinging from 0 to 5V at Mhz rates? It's better to attenuate this and give it a biased voltage, so that it swings up and down for 0.5V right in the region it is required by the chip. This decreases on-chip interference of the signals.
What chip does internally - if it has the same thing going on inside too - I don't know. But even if it does it internally, I guess it's better to do it externally anyway - lesser signals entering the chip mean less intermodulation regardless.
This all makes sense, and you can imagine that the input signal is dumping excess signal into the supply rails through resistors and diodes within the chip.
How audible this is I've yet to discover until I install the attenuators on my dac.
However, I do wonder that if this is a significant issue, why does digital technology not use the same approach. As far as I know, computers, phones, and other multi media devices do not have to resort to attenuation even though the switching thresholds are well above ground and below the supply rail.
You'd have thought that digital signals generally, would always be no more than say 80% of the supply voltage, eg 0.5 to 4.5 in a 5v circuit , or 3v p-p in a 3.3v system.
I guess there is always a downside - without attenuation there is more on-chip interference, with attenuation there is additional noise injected from diodes and resistors.
I agree the best way is to try it and if one way is a lot better, then it's clear. If it's all the same then it doesn't really matter, does it?
This might also depend on the frequencies, because higher freq bring more distortion and more easily intermodulate (oversampling, running DEM clock at 5,6MHz) and in this case attenuation might bring better results than in a plain NOS with dem running around 200-250kHz. I'm just guessing.
So maybe different solutions work better for different people and they can have different opinions and both be right.
I agree the best way is to try it and if one way is a lot better, then it's clear. If it's all the same then it doesn't really matter, does it?
This might also depend on the frequencies, because higher freq bring more distortion and more easily intermodulate (oversampling, running DEM clock at 5,6MHz) and in this case attenuation might bring better results than in a plain NOS with dem running around 200-250kHz. I'm just guessing.
So maybe different solutions work better for different people and they can have different opinions and both be right.
I2S attenuation brings an evident sonic improvement for the TAD1543 at least.
It can be referenced to an exclusive PS or connected as per the last recommendation from -EC- to the same PS(5V) with Oscon cap. I used either way and it went OK.
My present recommendation for TDA1543 is DUAL-MONO (6.5 TO 7.5V supply) for two towers of 8 DAC chips (16x current; 130 Ohm honeycomb I/V resistor), which gives a more detailed, raw and "live event" dynamics.
I tested -EC-'s "nul offset" circuit and, as always, he was right: it gives a more transparent and even more dynamic sound. Yet I have to get sturdier, more stable power supply to get a 0V offset, and, as I use dual-mono, I have to replicate the circuit for the other tower: due to tolerances, offsets are slightly different. I use TVC so I need truly 0V. For other systems, it is OK like it is now.
I'm off for vacations
Cheers!
M.
It can be referenced to an exclusive PS or connected as per the last recommendation from -EC- to the same PS(5V) with Oscon cap. I used either way and it went OK.
My present recommendation for TDA1543 is DUAL-MONO (6.5 TO 7.5V supply) for two towers of 8 DAC chips (16x current; 130 Ohm honeycomb I/V resistor), which gives a more detailed, raw and "live event" dynamics.
I tested -EC-'s "nul offset" circuit and, as always, he was right: it gives a more transparent and even more dynamic sound. Yet I have to get sturdier, more stable power supply to get a 0V offset, and, as I use dual-mono, I have to replicate the circuit for the other tower: due to tolerances, offsets are slightly different. I use TVC so I need truly 0V. For other systems, it is OK like it is now.
I'm off for vacations
Cheers!
M.
hi ec designs
It contains many innovations, USB, CPU, and DAC timing signals are all derived from a single local masterclock (single time domain operation).
I've seen this done all over the place - including on very basic micro-controllers like the Atmel tinyAVR. They way he is doing it might be novel, but deriving other clocks from your system master clock (CPU clock) is more common than not. And how good it is lives or dies on a number of factors not directly in "your" control. How good is that master clock in optimum conditions? How sensitive to thermal variation? What compensations are in place for this?
Time domain dithering is applied, it has similar effect on sound like dithering applied after reducing resolution (CD recording).
Where is this applied? As my first suspicion is that it's an attempt to compensate for generally poor clock stability/accuracy.
So we end up with higher perceived resolution and there is no longer the need for sample rates above 96 KHz.
I strongly suspect that it's not a case of "no longer need" and much more a case of "couldn't get it to function reliably". But, it's not clear if this is specifically a limitation from the USB perspective (since that's being done via polling) or the derived sample-clock, so who knows? That, or it's weasel-words for a decision to only support UAC1 so they didn't have to write drivers for Windows.
The major problems with I2S are the high interference energy levels (symmetrical square waves with form factor 1)
Now I really want to know what micro-controller is being used here as it is quite likely that it's a vastly more problematic offender for that sort of thing. Its one reason why the massively over-powerful XMOS and Amanero SoCs can cause issues if not treated sensibly (and they almost never are).
hi ec designs
It contains many innovations, USB, CPU, and DAC timing signals are all derived from a single local masterclock (single time domain operation).
I've seen this done all over the place - including on very basic micro-controllers like the Atmel tinyAVR. . How good is that master clock in optimum conditions? How sensitive to thermal variation? What compensations are in place for this?
Time domain dithering is applied, it has similar effect on sound like dithering applied after reducing resolution (CD recording).
Where is this applied? As my first suspicion is that it's an attempt to compensate for generally poor clock stability/accuracy.
So we end up with higher perceived resolution and there is no longer the need for sample rates above 96 KHz.
I strongly suspect that it's not a case of "no longer need" and much more a case of "couldn't get it to function reliably". But, it's not clear if this is specifically a limitation from the USB perspective (since that's being done via polling) or the derived sample-clock, so who knows? That, or it's weasel-words for a decision to only support UAC1 so they didn't have to write drivers for Windows.
The major problems with I2S are the high interference energy levels (symmetrical square waves with form factor 1)
really want to know what micro-controller is being used here as it is quite likely that it's a vastly more problematic offender for that sort of thing. Its one reason why the massively over-powerful XMOS and Amanero SoCs can cause issues if not treated sensibly (and they almost never are).
Any Mosaic-UV owners here?
Hi folks, I would really like to here from the owners of the first batch of Mosaic-UV buyers, ive done a few searches and found none, yet the first run sold out in a few days. I have just purchased a Schiit Gungnir multibit, its opened my ears and eyes to the effect a well designed DAC can have on my music, I wish I had seen Johns design first though. I will not be able to afford both for comparison so as so many do I would like to here from current owners before I bite the bullet and sell the Schiit, its the first product ive heard in more than a decade that has made me sit and listen to music again. (thanks to a new speaker and amp purchase)
Hi folks, I would really like to here from the owners of the first batch of Mosaic-UV buyers, ive done a few searches and found none, yet the first run sold out in a few days. I have just purchased a Schiit Gungnir multibit, its opened my ears and eyes to the effect a well designed DAC can have on my music, I wish I had seen Johns design first though. I will not be able to afford both for comparison so as so many do I would like to here from current owners before I bite the bullet and sell the Schiit, its the first product ive heard in more than a decade that has made me sit and listen to music again. (thanks to a new speaker and amp purchase)
I have a schiit yggdrasil and the mosaic T
will also buy the Mosaic UV when it comes out and get it in here!
ill report then