Building the ultimate NOS DAC using TDA1541A

The treble boost is necessary since the Dac is reconstructing the analog signal with square steps and not infinitely short pulses at the sampling instants.

Rectangles in the time domain having the spectra of a sinc functions in in the frequency domain having more energy content at low frequencies, thus you need to apply the inverse of a sinc in the frequency domain to get a summed flat frequency response.

If you are using 1.5K I/V resistors you can use a 8.2mH inductor in series with the I/V resistor and 3.3nF across the R-L combo to form a resonable accurate sinc compensation filter.

If you have an analog anti aliasing filter you can modify it by adjusting the Q as s3tup says to get some sinc compensation, you can use the R+L//C combo above as a model to mimic across the audio band.
 
You could avoid the need of sinc related treble boost by using an approximation of infinitely short pulses. Such pulses can be produced by a differentiating C-R circuit. The energy content will be very low after this circuit, that effect can be partly compensated by using high supply voltage (with a tube circuit). Another advantage of this circuit would be the natural insensitivity to jitter.
 
Too expensive, too low resolution (A/D conversion), and it doesn't capture the information I am interested in.

I reviewed your interferences.
The 2,5 kHz interferences are only ca. -16 dB below the 50 Hz.

Even the worst playtoy analyzer with 8 bit resolution = 48 dB dynamic range will show that and many more things you can not see with your scope.

As far as I know, energy from various sources is bundled together in the net, even from foreign power plants on demand. Either one of these sources is dirty or you have a big maschine somewhere in a factory spoiling the energy net.

Anyway, the 2,5 kHz will be smoothed out 99% by the first cap in your psu.
Can you still measure it after a simple regulator ?
 
Hi -ecdesigns-
At the beginning of this thread I was focussing on sample amplitude, smooth signals, low THD and so on. This resulted in the DI system that smoothens the NOS DAC output signal.

I supposed that you interest in the first place quality of the sound, rather then «
sample duration and sample shape».

This has resulted in reverting to one DAC chip, placing main focus on sample duration and sample shape.
You wrote that with increase the chip number sound became much clearer, detailed (for instance, posts #1, #9, #73 and so on). Was this an illusion?

Serg
 
Hi -ecdesigns-

I supposed that you interest in the first place quality of the sound, rather then «
sample duration and sample shape».


You wrote that with increase the chip number sound became much clearer, detailed (for instance, posts #1, #9, #73 and so on). Was this an illusion?

Serg

Audio is an illusion :checked:

A DAC signal that passes a brickwall filter is a smooth signal.
Everything else is :censored:
Ok. Everything else is a staircase.

And before EC will teach me that a brickwall is not acceptable for highly transparent sound because many reasons and his many listening tests...
( But a staircase is... because the speakers... and the ear... )

I did listening tests too. With a different result.

Fact is: Unfiltered nonos is a staircase signal with hf loss.
 
Here is my ac power one day.

I have a 16 bit plugin but measurement is done with a 8 bit plugin.

It has spurious at 12,5 kHz and 13,8 kHz.

netz1.jpg




Next day clean.

netz2.jpg
 
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Hi SSerg,

I supposed that you interest in the first place quality of the sound, rather then «sample duration and sample shape».

Yes, at the beginning I focussed on perceived sound quality and signal shape.

You wrote that with increase the chip number sound became much clearer, detailed (for instance, posts #1, #9, #73 and so on). Was this an illusion?

This was the conclusion made many years ago when digital audio source jitter levels were rather high.

Now I make conclusions based on low jitter systems and I got much more critical.

As far as paralleling DAC chips is concerned, each DAC chip has tolerances, including tolerances in propagation delay.
Propagation delay also depends on chip temperature and supply voltage.

So when paralleling DAC chips, each DAC chip can have slightly different temperature and supply voltage.

The samples of each DAC chip will not arrive at the summed output at exactly the same time. This would translate to a "rattling" sound (asynchronous sample latching) instead of a single click (synchronous sample latching).

This effect alone will significantly increase timing errors (jitter). So this type of DAC is more "compatible" with high jitter sources.
 
Hi -ecdesigns-,
Now I make conclusions based on low jitter systems and I got much more critical...
As far as paralleling DAC chips is concerned, each DAC chip has tolerances, including tolerances in propagation delay...
So this type of DAC is more "compatible" with high jitter sources.

Well
, that we have? Mountain gave birth to mouse.
The result of the gigantic thread became the confession to fallaciousness of initial ideas.

I'm sad.

Serg
 
Thomas Edison ran 11,000 experiments before he perfected the light bulb. Billions of people have benefited from his persisent journey. I for one have appreciated the journey that ecdesign has shared with us. The ideas that lead to dead ends are equal in value to those that yield perfection. It is the process of discovery and continuous improvement.
 
This is not a forum for dialectic confrontation but for inventing, sharing and building nice gear to enjoy our beloved music. People who contribute freely to our enjoyment must be thanked and encouraged...

John has explained most or all of his decisions and he declared at each major change why the former project was surpased by the later so the former was dissmissed and abandoned.
I don't think anybody has to write a long statement as mea culpa and strike his chest every time a project does not lead to an optimal outcome. There are things that are obvious and don't need to be written down to be understood...
 
And don't forget the principles described in the initial post (and the details in the subsequent first couple of posts) are way much better than found in most commercial DACs. Even if someone has different ideas, he still could learn a lot from this thread (or come along with his better solution - if there is any).
 
I've tried going through the posts, and found a few informative posts but I still need some clarification re the tda1541a grounding. The datasheet has the DEM caps to a ground, then a 100N cap' tied to ground from the -5 to -15V pins. The tech data has power supply rejection ratio -58db on -15V -84db on -5V.

The datasheet also lists 5V decoupled to joined analogue and digital ground yet says -0.3V to 0.3V difference between the analogue and digital grounds.

I suppose what I'm asking is are there two grounds required? My first thoughts were where do those DEM cap grounds go?

Appologies for any lack of understanding in advance!
 
Hi ash_dac,

I've tried going through the posts, and found a few informative posts but I still need some clarification re the tda1541a grounding.

Pin 5: analogue ground, this includes ground for active divider decoupling caps.

Active divider decoupling caps require -separate- GND route to pin 5. Active divider decoupling caps need to have low inductance (SMD film caps) and must be placed as close to the TDA1541A pins as possible, underneath the chip. Active divider decoupling cap value: 1uF, free running DEM oscillator frequency: 60 KHz (approx. 1nF between pins 16 and 17).

Pin 14: digital ground, reference for I2S input signals.

Local power supply decoupling:

Use 1uF SMD film (1210 size) in parallel with 220nF NPO, locate the decoupling caps underneath the chip for shortest possible wiring (lowest induction, most effective decoupling). The NPO cap is soldered directly to the PCB, the film cap is soldered directly on top of the NPO cap.

Capacitor between +5V and analogue ground.
Capacitor between -5V and analogue ground.
Capacitor between -15V and -5V.
Capacitor between -15V and analogue ground.

Un-interrupted ground plane is essential.

Analogue ground and digital ground are connected to the ground plane.
 
I've found some SMD 1uF caps (1210 size) that could fit for active divider decoupling.
They all are 16V, is this safe?
Better a PPS (polyphenylene sulphide) or FCA (acrylic) dieletrcic?
All other types (higher voltage, different dielectric) are too big for soldering directly on the pins of the TDA1541.
 
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