Building the ultimate NOS DAC using TDA1541A

4 years after I first started reading this thread and it's still WOW...

My DEM circuit failed the other day and started getting low level noise on my 4x 1541s1 linear interpolation dac... Fixed it and figured I would check see what you all are up to. ....

And you are still pushing the state of the art.... KUDOS to John and all of you....

JohnK
 
SD8 Transport

Hello John,

what is the present status of the SD8 Transport and when will it be available.
Can You provide a sketch with the location of the drilling holes and connectors (esp. I2S connector)?
What is the current consumption of the 3V3 supply?
To prepare my own DAC for the SD8 transport I have the following questions: What clock driver do You recommend for the 11.2896MHz clock to the SD Transport?
For the 14 filter caps can I use Cornell Dublier 1uF/10V in 1206 case?
 
Hi roger57,

One possible way to synchronize the DEM oscillator with WS is the following:

1.8nF 1% film or NPO cap between pins 16 and 17 (DEM oscillator runs on timing cap).
330nF film cap in series with 22K between WS and pin 16 (synchronization circuit).

Filter cap value (14x) 1uF.

Buffer is not required.

Has anyone implemented the above designs? I have now implemented it and overall it sounds very good. However, I did notice a very slight digital distortion on very low level signal (amplified of course by subsequent stages).

The distortion is much much less than the distortion there is when there is no DEM lock. Can the ones who have implemented this have a really good listen?
 
Has anyone implemented the above designs? I have now implemented it and overall it sounds very good. However, I did notice a very slight digital distortion on very low level signal (amplified of course by subsequent stages).

The distortion is much much less than the distortion there is when there is no DEM lock. Can the ones who have implemented this have a really good listen?


Hi Marten,

I have and found it to be very good :D
Since I like decent volume when I listen, I have yet to hear the artifacts you speak of. I do have a bit of a concern...John selected his words carefully and said "...one way to implement this..." As with anything in electronics, there more than one way to do something. Is this the best way? What are the tradeoffs of a different approach? Since John is well versed in fully understanding the DEM circuitry, there's a good chance he knows more than one way. I guess it's up to us to figure out others.
You might try trimming your clock & signal amplitudes back ( as John had recommended previously) to ensure they don't overdrive the delicate substrate in the chip as this will lead to distortion. I would experiment with a small pot on the clock/data lines to see the impact.

Keep us posted and I'll do the same :)
Gary
 
Has anyone implemented the above designs? I have now implemented it and overall it sounds very good. However, I did notice a very slight digital distortion on very low level signal (amplified of course by subsequent stages).

The distortion is much much less than the distortion there is when there is no DEM lock. Can the ones who have implemented this have a really good listen?

I changed from BCK>WS synchronisation for DEM on the way ECdesigns suggested. My listening experience is that there seems a little improvement in black background and less distortion. On the other hand it keeps on my mind that the timbres of instruments sounds less 'real' then with WS sync. I should make a switch to figure this out...
 
I use a free running DEM oscillator with timing cap. I reduced capacitor value so it oscillates around 3 MHz, it is then synchronized -not triggered- with the bit clock BCK (2.8224 MHz). So DEM clock jitter basically remains similar to a correctly functioning free running DEM oscillator. In order to meet 1% frequency stability, the DEM clock should not fluctuate more than 28 KHz or 35us peak to peak jitter. In practice it is no problem to achieve much lower values, this means I fully meet the conditions to stay well below 0.25 LSB error.

But this absolutely untrue! You do not are friends with mathematics, colleague!
The Frequency 200 KHz corresponds to the period 5us. 1% it is necessary to take from these 5us (getting herewith 50ns!), rather then from 2кГц, translating them then to 500us. 50ns and 500us - a great difference, not so?

The similar mistake you allow repeatedly. Here is example from the same post:

In order to meet 1% frequency stability, the DEM clock should not fluctuate more than 28 KHz or 35us peak to peak jitter. In practice it is no problem to achieve much lower values, this means I fully meet the conditions to stay well below 0.25 LSB error.”

You count so:
2,8 MHz*1%=28 KHz; 1/28 KHz = 35 us
It is necessary to count so:
1/2,8 MHz = 35 ns; 35 ns*1% = 0,35 ns
These errors are particularly vexatious because as a whole you write the sane belongings.

With best wishes
Serg
 
Hi, -ecdesigns-!

I have read begin this subject (thread interesting, but very big) and I faced the statement that your method Direct Interpolation allows to enlarge the resolution to 17 bits for twin DAC 1541 and to 18 bits for quad DAC 1541 (post #15).

You hitherto so think?

Respectfully yours


Serg
 
Hi SSerg,

I have read begin this subject (thread interesting, but very big) and I faced the statement that your method Direct Interpolation allows to enlarge the resolution to 17 bits for twin DAC 1541 and to 18 bits for quad DAC 1541 (post #15).

You hitherto so think?

The input resolution remains 16 bits, the time resolution is increased (88.2 KHz sample rate with 2 chips, 176.4 KHz with 4 chips, 352.8 KHz with 8 chips). The extra samples are derived using linear interpolation (delay and add scheme).

Output bit resolution is theoretically increased to 17 bits (2 chips), 18 bits (4 chips) or 19 bits (8 chips). In practice the output resolution is limited by DAC chip bit errors and matching between DAC chips.

The result is a smoother output signal (oscillograms at the beginning of this thread) when using NOS. This in turn improves performance when using (pre) amplifiers and interlinks that were designed for use with analogue audio sources.

Linear interpolation causes trebles roll-off in combination with NOS. The wave form starts to resemble triangle wave shape at increasing frequency when fewer samples are available for reconstruction.

However it works fine when applied after digital filtering. This technique is applied in the Cambridge CD3 CD player in order to achieve 16 times oversampling using 4 x TDA1541A.
 
I still love the 4x 1541 s1 direct interpolation NOS dac....treble role off does not matter to me. I don't know of a TT that will do a better job at the top end....

OS DACs produce artificial sine waves at high frequencies... You run out of samples in the source no matter.... Is it an 18k squarewave or sinewave? You will never know.

Jk
 
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Output bit resolution is theoretically increased to 17 bits (2 chips), 18 bits (4 chips) or 19 bits (8 chips). In practice the output resolution is limited by DAC chip bit errors and matching between DAC chips.

Hi,-ecdesigns-
Thank you for fast reply.

Output analog signal can't have more information than had the input digital signal. Even theoretically.

The practical resolution 1541 not more than 15 bits. At the best you may obtain resolution 16 bits.

This as law of the conservation
of energy.

Respectfully yours



Serg
 
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Hi SSerg,

Output analog signal can't have more information than had the input digital signal. Even theoretically.

I mentioned this:

The result is a smoother output signal

I didn't mention that we get more information out than we put in. I just mentioned that the output sample rate can be increased to 88.2, 176.4, or 352.8 KHz and that the output bit resolution can be theoretically increased to 17, 18, or 19 bits.

The gained output resolution is used for smoothing the NOS DAC output signal.

I attached some oscillograms. Upper traces show plain NOS DAC output signals, lower traces the same signal but now with 8 times linear interpolation (8 * TDA1541A). These show the desired smoothing effect.
 

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