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Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
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Old 16th May 2018, 12:53 PM   #6101
ecdesigns is offline ecdesigns  Netherlands
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Hi Alexandre,

Quote:
John, if one wishes to experiment with synchronous DEM clock would there be any benefit in using an attenuator before the DEM pin (like the ones used for the I2S inputs)?
You need roughly 1 ... 2Vpp trigger signal amplitude for reliable triggering. This will inject considerable switching noise.

I attached a close up of the Simultaneous interface switching noise that manages to leak to the TDA1541A output. This is an amplified TDA1541A output signal.

I have 1K series resistors on DOL, DOR, and BCK. LE is directly injected for lowest trigger uncertainty.

You can see the 16 bit data burst & bit clock noise (the spikes you see in the low level measurement). Then 16 bit silence (no bus activity), we can see that ground-bounce now reaches zero.

Then the outputs are latched with LE (spike) followed by 48 bits silence. Then the next sample is clocked in the same way.



We would get similar extra switching spikes on the output when triggering the DEM oscillator with 1 ... 2Vpp.

With 50Hz DEM we have one switching spike every 882 samples. With 200 KHz DEM we have 4.5 spikes in each sample. This illustrates the impact of high DEM clock rates, every sample is distorted by the spikes generated by the free running 200 KHz DEM clock regardless of decoupling. This is switching noise (ground-bounce) generated on the chip, out of reach for external corrections.

The TDA1541A is based on -silent- current steering logic (comparable with ECL). So it won't get much better using modern CMOS logic that produces more switching noise compared to ECL.
Attached Images
File Type: jpg SIMgroundbounce.jpg (83.5 KB, 508 views)
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Old 16th May 2018, 04:42 PM   #6102
esgigt is offline esgigt  Netherlands
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@ECdesigns


John, thanks for explaining and the scoop screenshots. It's much clearer now.
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Old 17th May 2018, 07:44 AM   #6103
Hanze Khronye is offline Hanze Khronye  Australia
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I'd like to ask again with regard to the biasing of the DEM to -15V, how this can be achieved to both pin 16 and 17 equally, when there is a DC blocking capacitor between them, unless two separate resistors are used?.
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Old 17th May 2018, 07:53 AM   #6104
weissi is offline weissi  Austria
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From what I know, the basic DEM oscillator is based on a FlipFlop (Multivibrator): https://upload.wikimedia.org/wikiped...brator.svg.png
If we assume that C1 is the cap that is accessible over the Pinout, I could imagine that you'd only need to bias the base of transistor T2.... But that is only my guessing.
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Old 18th May 2018, 08:47 AM   #6105
JOSI1 is offline JOSI1  Germany
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DEM, Simultaneous protocol converter

Hi John,

what family did you use for the single gates 74LVC1Gxx ??

In the present DEM I use 470n SMD film CAPS soldered directly under
the TDA1541A chip. When changing to 50Hz-DEM with 100uF-Elkos
is it better to remove the 470n film caps or keep them in parallel.

Thanks
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Old 19th May 2018, 12:14 AM   #6106
Hanze Khronye is offline Hanze Khronye  Australia
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Quote:
Originally Posted by weissi View Post
From what I know, the basic DEM oscillator is based on a FlipFlop (Multivibrator): https://upload.wikimedia.org/wikiped...brator.svg.png
If we assume that C1 is the cap that is accessible over the Pinout, I could imagine that you'd only need to bias the base of transistor T2.... But that is only my guessing.

Thanks for this..


WRT the linked diagram, the connecting pins are for DC voltage supply to the circuit, which is different from what is happening at pins 16,17 of 1541A.


Given the scarcity of 1541A's, that 16 and 17 to -15V via 6k8 (ea) works, and has both parts of that circuit at the same potential, I'd like to be sure about what is actually going on before blindly leaping toward an 'improvement'.


Perhaps John could elaborate for peace of mind..


Thanks.
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Old 19th May 2018, 03:21 AM   #6107
Alexandre is offline Alexandre
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Quote:
Originally Posted by ecdesigns View Post
You can see the 16 bit data burst & bit clock noise (the spikes you see in the low level measurement). Then 16 bit silence (no bus activity), we can see that ground-bounce now reaches zero.

Then the outputs are latched with LE (spike) followed by 48 bits silence. Then the next sample is clocked in the same way.
This was interesting to see. Was that measurement done by probing directly at the I/V resistor, or with an amplifier?

I wonder if an even cleaner analog output could be obtained with something like the I/V I recently posted. Where the I/V resistor is referenced to +5V. The probe ground must be connected to +5V, of course.

Thanks,
Alex
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Old 19th May 2018, 01:33 PM   #6108
4rgroup is offline 4rgroup
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Quote:
Originally Posted by ecdesigns View Post
And now the practical 24 bit Left Justified to Simultaneous protocol converter circuit.

With LJ format the Right channel data is present when WS is low and the Left channel data is present when WS is high. With I2S the Left channel data is present when WS is low and the Right channel data is present when WS is high.

The 24 bit left justified interface signals DI (Data Input), WSI (Word Select Input), and BCKI (Bit Clock Input) enter the circuit at the top left.

First we have to identify and invert the MSBs. With LJ format we know that the MSB comes immediately after a WS change. U1, U2, and U9 create a delay that equals exactly one bit.

This works as follows, U1 delays the WSI signal for half a BCKI clock period. U2 receives an inverted BCKI signal and delays WSI for another halve BCKI clock period. Total delay is now -exactly- 1bit.


When we XOR this signal (U2 pin 4) with WSI we get a positive pulse the moment MSB occurs in the stream, immediately after a WSI change.

XOR gates can be used to invert a signal. When we put a "1" on the control input the signal on the other input is inverted. When we put a "0" on the control input the signal on the other input is not inverted.

When we XOR this pulse with the DI signal we can invert MSB only as the inversion only occurs during the short moment the MSB identifier pulse goes high. I combined two XOR gates by using a 3 input XOR gate. If this is a problem one can combine U2 Q output with WSI in a 74HC86 and then combine the output of this 74HC86 with DI using a second 74HC86 XOR gate. The output of that second XOR gate is connected to U3 D input.

Ok so we inverted MSB on the fly for both L and R channels.

We will need data delay circuits and in order to phase align both L and R channel data we start with flip-flop U3 so we can clock out both L and R channel data on the same BCKO clock edge.

We now have the DOR signal present on U3 pin 4.

The Left channel can now be aligned by adding 32 bit delay (U5 ... U8) and now we have DOL data on U8 pin 13.

The remaining thing to do is disabling DOL, DOR, and BCKO for the remaining 48 bits.


U4 is a counter that only counts when WSI is low (RST = 0) After 16 pulses its output Q4 (pin 5) goes high and when we NOR this signal with WSI we get a window signal that is only "1" when the 16 data bits are clocked out.

This window signal drives 3 AND gates U12, U13, and U14 that force these signals to "0" after the 16 bits have been clocked out.

The WSI signal is simply fed through and occurs at the output as the LEO (Latch Enable Output) signal that latches the TDA1541A outputs (simultaneous mode) on the -rising- edge of BCK.


The circuit consumes very little power, simple LED (L1) and diode(D1) shunt offer approx. 2.4V supply voltage (VDD) so we don't need attenuator circuits and we have low switching noise in the protocol converter circuit.
Hi ecdesigns,
I confuse ICs with ICs in your picture (http://www.diyaudio.com/forums/attac...1541a-pcv1-jpg)

Could you help correct my list of ICs
1) U1, U2, U3 (74G79) can be The D-type Flip Flop MC74HC74A from ON Semiconductor
2) U9 (74G04) can be the Hex Inverter PO74G04A from PotatoSemi
3) U12, U13, U14 (74G08) can be the positive-AND gate PO74G08A from Potato Semiconductor
4) U10 (74G386) can be the Exclusive OR Gate 74HC86 from PotatoSemi
5) U4 (74HC4060) can be the 14-stage binary ripple counter with oscillator 74HC4060 from Nexperia
6) U5, U6, U7, U8 (74LV164) can be the 8-bit serial-in/parallel-out shift register 74LV164 from Nexperia

Thanks and Regards.
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Old 19th May 2018, 04:48 PM   #6109
ecdesigns is offline ecdesigns  Netherlands
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Regarding the Logic family for the protocol converter.

74LVC1G79, 74HC74 (D flip-flop, outputs not inverted, separate clock inputs)
74LVC1G04, 74HC04 (inverter)
74LVC1G386, 74HC86 cascaded (3 input XOR gate)

Output of XOR gate #1 goes to one input of XOR gate #2. Use 3 remaining inputs.

74LVC1G08, 74HC08 (2 input AND gate)
74LVC1G02, 74HC02 (2 input NOR gate)
74HC4060 (counter)
74LV164, 74HC164 (shift register)

Brand is not critical, speed must be higher than CD/HEF 4000 series.

74HCT family can also be used if the supply voltage is increased to 5V.
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Old 20th May 2018, 07:13 AM   #6110
ecdesigns is offline ecdesigns  Netherlands
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Default DIR9001+protocol converter module for TDA1541A

Here is a picture of a completed DIR9001 S/PDIF receiver & protocol converter module. It can directly drive a TDA1541A through the simultaneous interface. It is basically a combination of the Toslink receiver plus protocol converter schematics I posted.

This is perhaps the easiest and cleanest way to drive a TDA1541A in simultaneous mode as the discrete low power logic produces very little interference compared to a CPU, ASIC or FPGA. It also supports battery powered operation for a very clean off-line power source.

TDA1541A is added in order to get an impression of the module size.


It is powered by a 3V4 ... 5V external (battery) power supply. On board ultra low noise LP5907-3V3 LDO regulator.

Idling, 13mA, 42.9mW
Streaming 44.1, 15mA, 49.5mW
Streaming 48, 16mA, 49.5mW
Streaming 88.2, 22mA, 72.6mW
Streaming 96, 23mA, 75.9mW

LED lock indicator.

Power supply and LED can be connected to the 4 solder pads on the side of the PCB

3.5mm Toslink input, 44.1, 48, 88.2, 96 KHz.

The DIR9001 is set as follows:

Clock source: PLL.
Format: 24 Bits, Left Justified.
SCK frequency, 256 fs.

Digital interface Output signals:

DOL (Data Out Left channel) for TDA1541A.
DOR (Data Out Right channel) for TDA1541A.
BCKO (Bit Clock Output).
NBCKO (Inverted Bit Clock Output for TDA1541A).
NWIN (Inverted Window signal).
WIN (Non Inverted Window signal).
LEO (Latch Enable Output for TDA1541A).

The extra output signals may come in handy when interfacing to DAC chips other than the TDA1541A.
Attached Images
File Type: jpg spdif-pcv1.jpg (157.4 KB, 318 views)
File Type: jpg spdif-pcv3.jpg (129.6 KB, 308 views)
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