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Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
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Old 10th April 2018, 08:07 AM   #6061
zenelectro is offline zenelectro  Australia
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Just an idea - what about using a high speed BJT follower after the logic gate. An RF BJT will have from <1pF to 2pF load on the logic and it will have lower OP Z of a few ohms or less if you load it with more current.

This would be very easy to implement and the extra class A loading could be a simple resistor to a - supply.

T
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Old 10th April 2018, 08:58 AM   #6062
ecdesigns is offline ecdesigns  Netherlands
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Hi andrea_mori

Quote:
just a curiosity about ternary logic switches, are you using discrete devices or logic IC (flip-flop, latch) like Soekris or Rockna's devices?
I use 7400 series bus storage registers for the Mosaic UV and 7400 bus storage registers and 7400 series octal D flip-flops for the Mosaic II. These are similar devices as used in most discrete R2R ladder DACs.

Quote:
I have not yet decided which is the best way, there are advantages and disadvantages in both cases. With discrete parts you can reach very low RDS-on (20-30 mOhm or so), but they are slower that logic ICs. Also the logic to drive discrete switches is more complex and p-channel devices are tipically different from n-channel devices (RDS-on, input and output capacitance, speed).
Conversely logic ICs are simpler to drive, are faster but have greater RDS-on (10 to 20 ohm or so), that finally affects the ladder network precision (monotonicity).
We have to face the fact that there are no perfect components, ok we might get parts with say 1 Ohm RDSon but these will cause new problems (higher surge currents, higher ground-bounce, more pollution) especially with the given parasitics of a relatively large discrete circuit.

The same imperfect devices can be used in different ways to improve performance. The Mosaic converter circuit -looks- similar to conventional discrete R2R ladder DAC circuits, except, it is no R2R ladder DAC.

Most popular discrete R2R ladder DACs are based on simple voltage attenuators based on two resistors (R and 2R).

For higher precision Wheatstone bridges are used:

Wheatstone bridge - Wikipedia

That's what I used for the Mosaic matrix converter and that's why accuracy is no longer an issue.

The remaining small bit errors are below the audibility threshold. These errors can be easily nulled by trimming.


I personally would be much more concerned about the (interface) noise spectra that are unavoidable with digital audio.
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Old 10th April 2018, 09:13 AM   #6063
Alexandre is offline Alexandre
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Hi John!

I just wanted to point that I mentioned you, and your research, in a recent post... here:
Integral nonlinearity (INL), THD, etc., in multi-bit DACs
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Old 10th April 2018, 11:12 PM   #6064
andrea_mori is offline andrea_mori  Italy
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Quote:
Originally Posted by ecdesigns View Post
For higher precision Wheatstone bridges are used:

Wheatstone bridge - Wikipedia

That's what I used for the Mosaic matrix converter and that's why accuracy is no longer an issue.

The remaining small bit errors are below the audibility threshold. These errors can be easily nulled by trimming.
Well, I have a little preference for the discrete devices.
They have some drawbacks but since they have to switch at a relatively low frequency (44 to 192 or maybe 384kHz) they are not so bad.
In the attached picture the simulation (48kHz and 384kHz) and the real measurement (45 kHz and 443kHz) of a mosfet pair in SO-8 package.
The waveform is beatiful at 45kHz and still looks good enough at 443kHz. The ground bounce can be decreased with a better driver circuit.
The advantage of this configuration is that they have very low output impedance, 38 mOhm for the N-channel and 66 mOhm for the P-channel, that means less than 0.001% with a 10K ladder (17-18 bit accuracy).

BTW, I can't figure out how a Weathstone bridge can help with DAC accuracy. You need anyway precise resistors to balance the bridge (or to unbalance it at certain current/voltage) unless you trim individually each bridge or you use some artifacts to get a dynamic correction of the error due to the resistances tolerance.
Moreover, let say a 74LVC574 has an output impedance around 23 Ohm when it switches low and around 25 Ohm when it switches high, at least 350 times higher than the mosfet pair. This resistance is in series with the ladder, so with a 10k ladder it weights at least 0.25%.
This resistance could be part of the bridge so it does not affect the balance, but:
- the other resistances of the bridge have to be very precise
- there is anyway a difference around 2 ohms between the low/high logic states (at least 0.01% with a 10k ladder)

What is missing?
Attached Images
File Type: jpg Sim_Mosfet_pair_48kHz.jpg (77.0 KB, 675 views)
File Type: jpg Sim_Mosfet_pair_384kHz.jpg (78.1 KB, 656 views)
File Type: jpg Mosfet_pair_45kHz.jpg (17.7 KB, 656 views)
File Type: jpg Mosfet_pair_443kHz.jpg (18.7 KB, 650 views)

Last edited by andrea_mori; 10th April 2018 at 11:16 PM.
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Old 26th April 2018, 06:20 AM   #6065
ecdesigns is offline ecdesigns  Netherlands
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Hi andrea_mori

Quote:
They have some drawbacks but since they have to switch at a relatively low frequency (44 to 192 or maybe 384kHz) they are not so bad.
Slower logic in combination with parasitics causes unwanted glitches. Low RDSon in combination with parasitic capacitance and inductance causes ground bounce and ringing even before a resistor is attached.

What we need is fast logic that produces minimum ground-bounce and ringing. After testing many different logic family versions I ended up using fast logic with 8mA output current, RDSon high = 43 Ohms, RDSon low = 32 Ohms.

Best results at higher sample rates and lowest noise are obtained using lowest practical resistor values. In the Mosaic Matrix DAC I can go as low as 250 Ohm network impedance.

The Mosaic matrix converter is sensitive to resistor tolerances and RDSon high/low -mismatch- between driver circuits. However, before trimming the average bit error (80+ units tested) is already below the audibility threshold. After trimming -60, -70 and -80dB test signals look fine on the scope. Even dither patterns are clearly visible.

I used these test tracks for trimming:

Test CD



R2R ladder DACs are sensitive to resistor tolerances and absolute RDSon of the driver circuits.

There are ways to reduce RDSon related error in R2R ladder converters:

1) Calculate the average RDSon value (RDSon high + RDSon low) /2. With 43 and 32 Ohms we get 37.5 Ohm average RDSon. Subtract this value from the 2R resistor connected to the driver. For example when using 10K for 2R, we could add a high Ohmic shunt resistor so we get a new 2R value of 9962.5 Ohms.


2) Use two tri-state drivers for each bit. Enable one driver (/OE = 0) when data = 1 and the other driver (/OE = 0) when data = 0. Connect the inputs of the tri state drivers to VDD and VSS respectively. This requires an additional inverter to drive both /OE inputs.

Now connect a 10000 Ohms - 43 Ohms = 9957 Ohms resistor to the tri-state high driver and a 10000 Ohms - 32 Ohms = 9968 Ohms resistor to the tri-state low driver. Connect the other wire of both resistors together and to the ladder. Again high Ohmic shunt resistors can be used to get exact value.

This way it is also possible to compensate for RDSon low and RDSon high tolerances of each driver.
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Old 26th April 2018, 07:41 AM   #6066
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by ecdesigns View Post

I used these test tracks for trimming:

Test CD
Interestingly, a very scrupulous test. In what standard are the tracks made? 44,1/16?
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Old 29th April 2018, 11:02 PM   #6067
andrea_mori is offline andrea_mori  Italy
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Quote:
Originally Posted by ecdesigns View Post
Hi andrea_mori



Slower logic in combination with parasitics causes unwanted glitches. Low RDSon in combination with parasitic capacitance and inductance causes ground bounce and ringing even before a resistor is attached.
Hi John,

I'm not much worried about glitch, I use sign magnitude notation (so the MSB doesn't switch at every zero crossing), and also first 5 MSBs are thermometer docoded, so only a switch turns on at a time. Finally voltage output DAC helps to decrease the glitch.

Rather I'm a little worried about ground bounce and ringing, clearly visible in the plots I posted. So I'm investigating about the various flip-flop families.
Firstly I would say that a good practice should be using single flip-flop instead of multiple (octal or so on), to avoid any loop between the flip-flops. This should help to decrease the ground bounce.
Also, with single flip-flops I can install a bypass capacitor for each one, helping again to reduce the ground bounce.

There is not a great choice of single flip-flop with 3-state output: there is the NXP 74AUP family, very fast devices but very low current output (4mA at 3V) and very high RDS-On (around 100 ohms). Then there are the TinyLogic from Fairchild and the LVC family from TI, very similar, slower than the NXP but with much more output current (24mA at 3V) and lower RDS-On (23-25 ohms).
Time to do some tests.

On the accuracy side I believe that we need at least 16-17 bit. Since a RDS-On of 23-25 Ohms or more heavily affects the accuracy of the ladder network most part of the switches need fine trimming (at least first 16 MSB).
-60dB means 10 bit of accuracy, we need at least -90dB (16 bit).
In my design the first 5 MSB are not affected by the RDS-On of the active devices, because the thermometer decoder doesn't care about the resistance in series between the active device and the resistor of the ladder. Anyway I have to trim at least 11 bit, not a simple job.

The test tracks are very interesting, but why not to trim every bit in DC?
Using a 6.5 digits DMM one could switch one bit at a time measuring directly the DC voltage at the output.

Andrea
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Old 10th May 2018, 05:36 AM   #6068
ecdesigns is offline ecdesigns  Netherlands
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Hi andrea-Mori,

Quote:
Rather I'm a little worried about ground bounce and ringing, clearly visible in the plots I posted. So I'm investigating about the various flip-flop families.
Firstly I would say that a good practice should be using single flip-flop instead of multiple (octal or so on), to avoid any loop between the flip-flops. This should help to decrease the ground bounce.
Also, with single flip-flops I can install a bypass capacitor for each one, helping again to reduce the ground bounce.
The flip-flops should drive the /OE inputs of a tri-state buffer pair. One flip-flop, two tri-state buffers. Tri-state buffer #1 drives the 2R resistor that is compensated for RDSon high and buffer #2 drives the 2R resistor that is compensated for RDSon low. The buffer inputs (A) are connected to VDD and VSS respectively and the /OE inputs are driven by the flip-flop Q and /Q outputs.

The longer the traces between flip-flops and other circuits, the higher the trace inductance the more problems.

Anyway, designing and building a good discrete D/A converter is child's play compared to the many issues introduced by data timing and noise signals.

Also keep in mind that a significant number of LSBs will be masked by (ambient) noise, especially at lower (comfortable) volume settings.
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Old 10th May 2018, 05:55 AM   #6069
ecdesigns is offline ecdesigns  Netherlands
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What about a TDA1541A related post for a change

Some weeks ago I picked up the TDA1541A project again as DIY audio members asked for this. It resulted in a rather strange design that performs exceptionally well. I plan to publish schematics for DIY.

I needed some digital audio receiver to experiment with so I used a DIR9001 receiver board I designed for the Mosaic Toslink project. I configured it for left justified so it was easier to design a discrete protocol converter that outputs simultaneous data (Data Left, Data Right, bit clock and Latch Enable).

The advantage of simultaneous data is that we can have 48 bit silence after clocking in L + R data simultaneously. This greatly reduces on-chip ground-bounce. Now the outputs can be latched with a separate latch signal (LE) when ground bounce has reached zero so on-chip trigger uncertainty will be as low as it gets.

The protocol converter inverts the MSBs on the fly, lines up L and R channel data and creates short 16 bit data and clock bursts followed by 48 bit silence.

The protocol converter uses very little power (few milli amps) and runs on 2V4 so I don't need attenuator circuits on the digital interface inputs. It produces extremely low switching noise compared to an ASIC or similar programmable logic.

TDA1541A was placed in simultaneous mode (pin 27 tied to -5V).

And then there was the DEM circuit problem again, RF interference all over the place and poor low level performance. So I decided to try low frequency DEM. I set up the DEM oscillator for approx. 50Hz (1uF between pins16 & 17, 12K between pin 15 and 17 for bias). Yes, 50 Hz as in 50Hz mains frequency.

After some experimenting I ended up installing 14 x 100uF/25V for filtering. Plus goes to GND as the DC voltage on the decoupling pins is negative. These capacitors take up to 30 seconds to charge as these have to be charged with the low bit currents. There will be heavy distortion at power up that slowly disappears as the capacitors charge and start averaging the active divider output currents.

I was worried about DC leakage current and low level performance. However low level measurements showed very good low level performance even with a plain A chip all the way down to -80dB.

This simple DEM mod can be used with every TDA1541A-based design.


Decoupling is far less critical now as the highest frequency equals only 50Hz. The ripple voltage on all pins was too low to measure with my scope. The absence of continuous RF noise also makes the power supply less critical.

For passive I/V I use 150 Ohms, without further measures this leads to heavy distortion because of the negative DC offset caused by -2mA bias (0.002 * 150 = -300mV). I added a 2K2 bias resistor between output and +5V. Now I get low distortion 600mVpp at the TDA1541A output. This signal can either drive a sensitive (pre) amp directly or one can add a pre amp circuit like the Aikido tube or semiconductor amp.

One might connect multiple TDA1541A chips in parallel in order to lower the I/V resistor value.

Now one could drive a step up transformer while maintaining reasonably low output impedance (I/V resistor value times transformation ratio squared). This enables fully passive output with low enough output impedance to directly drive a (pre) amplifier.

Some examples:

One converter, 600mVpp 150 Ohms, 1:2 step-up, 1.2Vpp out 600 Ohms output impedance. 1 x TDA1541A for stereo
Two converters (dual mono), 600mVpp, 75 Ohms, 1:3 step up, 1.8Vpp out, 675 Ohms output impedance. 2 x TDA1541A for stereo
4 converters (dual-dual mono), 600mVpp 37.5 Ohms, 1:4 step up, 2.4Vpp out, 600 Ohms output impedance. 4 x TDA1541A for stereo.
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Old 10th May 2018, 10:51 AM   #6070
maxlorenz is online now maxlorenz  Chile
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Great simultaneous project. Thanks dear Guru.

Quote:
After some experimenting I ended up installing 14 x 100uF/25V for filtering. Plus goes to GND as the DC voltage on the decoupling pins is negative. These capacitors take up to 30 seconds to charge as these have to be charged with the low bit currents. There will be heavy distortion at power up that slowly disappears as the capacitors charge and start averaging the active divider output currents.
So they have to be high Q, low leakage. What about tantalum?

Now, where to find some chips from a reputed seller?

Best wishes,
M.
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