Well, I remember more useful debate from decade(s) ago. I went to QED and stand by that. Time for ignore I guess.
Thor
I'm sorry but this is now - if not even before - simply rude. You can make a case for your argument, it's a grown up world.
Well, actually looking at the datasheets and logic truth table should do.
Anyway, all this little petty bickering was caused with my opener to see if there was interest for an open sauce project to make a dedicated frontend with simultaneous output for TDA1541, using FI, FO, FUM, I think I smell an Englishman (couldn't resist), using FIFO IC's to reduce complexity and increase elegance over shiftregister based "inelegant, brute force" options.
That got totally lost and I hear crickets on the new tread I started...
Thor
With greetings from a night market at the Thai Riviera, drinking Rum and Coca Cola (from glass bottles) looking at a starry sky and eating an awesome steak for around 5 Bucks.
Listening to a blind one man band on a piano doing a great jazz/swing a cover of Robbie Williams "She's the One".
Life is good...
"'the players gonna play, play, play, play, play
And the haters gonna hate, hate, hate, hate, hate
Heartbreakers gonna break, break, break, break, break
And the fakers gonna fake, fake, fake, fake, fake"
This reminds me of Forrest Gump when Bubba finishes talking about shrimp and says "... that's.. that's about it"
Well, kind of. Analogue, power supplies, TDA1541 itself is a closed subject for me.
I have been looking around edges. Mainly the "frontend". A few things come up that are not covered here yet.
1) SPDIF Input?
It seems that AK4118 (for stuff not marked NRND) is the best choice for SPDIF receiver.
HOWEVER, it requires some care in implementation. Here the possible jitter Plot of an AK4493 driven from AK4118 MCK with the AK4118 used correctly:
Do it wrong, you get this:
So I think recovered Clock from AK4118 done right is good enough for a 16 Bit DAC. Available at JLCPCB for under 5 Bux and in stock.
In addition, I think I place this IC under a CS8412 DIP footprint, so WM8804/05 or others can be used as alternative on a piggyback PCB. Some resistor jumpers to switch off the AK4118 in that case.
2) How to do Isolated USB and clocking?
For ready-made stuff from Scheena the Amanero standard footprint with SPDIF is pretty much the "gold standard". You will be able to find many options. Others exist but cost is not reasonable.
As I will limit the maximum sample rate to 192kHz we can use the SPDIF output and isolate this. SPDIF is trivial to isolate, so we are limited to 192kHz, big deal. We use TDA1541 anyway and I have yet to find a native 352.8/384kHz PCM recording of Music I want to listen to for the Music's sake.
Disclosure - the later CD-77 with USB & SPDIF input used this with WM8805 in HW control mode and the DP-777 used the same, but using two WM8805 in software mode cascaded. The trick was to "freeze" the clock in the second WM8805 once locked in so it no longer changed and to use a CPLD with a memory buffer. Later we upgraded the firmware with a DDL frequency control. Anyway, that's just BTB.
The MCK is just as easy to isolate, I once designed a transformer coupled clock injector for a Superclock to connect to CD-players typical oscillator instead of a crystal. Simple LVC buffer into the transformer directly (Zsrc < 30R) terminated with a 220+110R divider. Worked very well and gave nice crisp edges at up to ~68MHz at the output of the inverter. So I'll just re-use this.
Relay switch over between AK4118 MCK set to 512X and the 512X MCK (transformer isolated) from the USB 2 SPDIF Bridge eliminates jitter down to MCK of the source plus divider/reclocker. All of the noise from dividers and noisy ground bounced CLPD/FPGA/CPU output pin's is ignored.
3) How to get the lowest continuous BCK Frequency in either SIM or IIS mode?
In SIM Mode the LE clock leading edge determines conversion timing, output registers are updated on the rising edge of LE. ONLY LE timing impacts on jitter on the analogue output. The BCK can be as low as 16 X FS. There is no "magick" in SIM mode. It likely bypasses some of the internal circuitry, but that is all ECL it is unlikely to make a material difference to Phasenoise/Jitter. The low BCK frequency (705.6kHz for 44.1kHz FS and 3.072MHz for 192kHz) allows us to slow the edges of BCK and Data (and WCK of course) WAY down. A rise time of 40nS will be more than adequate.
In IIS Mode the Bit clock leading edge determines conversion timing, output registers are updated on the rising edge of BCK. The BCK can be as low as 32 X FS. The 32X clock means we need twice as steep edges for for the clock, which will cause 6dB more feedthrough of BCK into the output, but in the CD-77 I could not substantiate any BCK presence. Anyway, we still are fairly low at 1.4112MHz at 44.1kHz and 6.144MHz at 192kHz. This means we need likely a rise time of around 20nS, but that would be to the trigger point.
If inputs are overdriven, input rise times are fast or we do not decouple +5V to -15V and DGND adequately, problems can couple between inputs and we may see additional jitter in the audio output in addition to digital noise. All of this is specific to TDA1541 and was discussed before. All considered, the slowest edges possible are preferred, this in turn means reducing the Bitclock frequency as much as possible. SIM Mode has a theoretical benefit here, as clocks can be lower and rise time slower.
I will simply use the values developed for CD-77 re-scaled as these were extensively tested. CD-77 used appx. 0.5V PP swing with ~ 12nS risetime or a slew rate of appx. 1V/24nS. As long as we keep the slope to a similar speed we should have outputs free from digital switching noise.
Back in the CD-77 I used IIS at 32X with the TI SRC419X both as converter from 64FS BCK IIS to 32FS BCK IIS and as (optional) 2X or 4X up-sampler. Looking back I see the choice validated. We have one IC, at modest cost (< 7 Bux for SRC4190 at JLCPCB fitted).
So we get a SRC419X operating synchronous (integer ratio between in/out) as format converter to 32FS BCK 16Bit IIS and optional upsampler/digital filter with the input and output in slave mode, so we create the BCK, WCK & DEMCK with our own dividers so we have complete control over jitter. As each division drops phase-noise by 6dB, once we divide from 512X for a 32X BCK for 192kHz we have lowered phase-noise/jitter another 12dB or so:
After looking at the various options for SIM I think I'll put a SAA7220 socket and a divider cascade for BCK, WCK, DEMCK and an SRC419X under the SAA7220 footprint.
Then the SAA7220 Socket can get a Piggyback PCB with either SRC419X, an FPGA/CPLD or whatever you like. The "whatever is on that board" stuff needs to allow the output to operate as slave, as most FPGA's, CPLD's and XMOS processors add 100's of pS of Phasenoise, which is why I do not want to use them.
In this case using 32XFS BCK is the much lesser compromise.
If I can get the FIFO based SIM converter discussed elsewhere going, this would be used instead.
4) What Clock Division Logic Family and Devices for lowest Jitter?
Somewhere over the rainbow, or was it in this thread, ecd and others discussed logic families and jitter.
Among the readily available logic series the 74F series is among the lowest for Jitter, not far off from 74AC. Best in principle is ECL but cost and complexity increase to a point where it becomes pointless. Internally, as remarked the TDA1541 is ECL but the TTL-2-ECL conversion on the input will have more jitter than all the rest. In the CD-77 I used ECL for drive and reclocking, but it is not really advantageous over simpler circuit and was slated to be replaced.
When comparing, bipolar dividers (74F, ECL) tend to have higher flatband phase noise, but a much lower 1/LF rise corner, meaning they do better on close-in jitter. I had some nice diagrams illustrating this, but I'm foxed as to where I left them, so you have to take my word. Modern low voltage CMOS logic has this problem more and more and even if RMS jitter is low (especially when measured above 12kHz) close in jitter is often not great. So really only 74AC logic at 3.3...5V or 74F logic should be considered other than ECL, based on the circuit noise.
Another factor is "ground bounce".
For CMOS IC's, which are comprised of "Complementary MOS" Inverters or more, each time an inverter or gate switches, we have an unavoidable current spike at the switching threshold. With fast enough edges and logic the spike while relatively high in current amplitude passes very fast (nS or so). But, each inverter or gate that is connected in series will add it's "spike" to the general cacophony of everything else switching.
As these currents will flow between supply and ground pin and are ABSOLUTELY UNAVOIDABLE, they will cause a voltage drop in the IC lead frame (and PCB in poor layouts). This is a big problem, as inputs and inverter's or gate's in general rely on the Mosfet threshold voltages which are referenced to ground pin (via inductance) for the N-Channel pull down device and to Vcc for the P-Channel pull up device. It means that when the ON CHIP rail or ground voltage shifts the trigger point shifts.
For generic CMOS 10mV noise equates to ~ 1pS jitter in a simple IC, like an inverter (for a clock oscillator). As 0.5V ground/supply bounce in the chip lead frame are not unheard off we are unavoidably adding data/clock dependent jitter in the 50pS region.
By comparison ECL is differential so there is no ground or supply bounce at all and F(ast Schottky) TTL circuits also have much less ground bounce as there is no "switching spike" from shoot through current and as technically the switching point is based on current flow, not voltage, inputs are less sensitive to ground bounce.
So, summa summarum, 74F series IC's are best suited for our clock divider, over 74AC and more modern IC's. The intended 512X (22.5792MHz/24.576MHz) Clocks are well inside the specifications.
We can use a 74F161 or 74F163 programmable counter to make a pin programmable divider with a division of 1-16. We still need another divide by 2 behind this, so 74F74 creates the actual 50% duty-cycle BCK and we can simply select the BCK as 32X of 1X, 2X & 4X Sample rate based on the MCK. Minimal jitter/phase noise. I have seen these dividers (as 74AC) in super low phase noise reference clocks. Another 74F161/163 & the second half of the 74F74 create the WCK from the BCK.
This divider chain would be for a SRC419X. It needs reconfiguring if we use another solution with SIM Out. Then BCK comes from the second 74F161 (we just cascade) and is divided down to 16X plus we reclock LE with the BCK. No real other change.
We also need a 8X DEM Clock locked to MCK. This means divide by 64 (24.576MHz/64 = 384). So two pcs of 74F161/163 or 1pcs 74HC4040.
We could use a second 74F74 to reclock Data (L/R or IIS) but I see little benefit from doing so. We just use the jittered Data at 3.3V P-P and attenuate and slew rate limit. There is no drawback I can see, we just need the data to arrive in the BCK window.
Thor
Here would be such a clock divider in detail.
A 74ACT125 Buffer is used to buffer the 74F161(163) input, as there is ~ 0.6mA flowing when the clock Pin is low, which are directed away from the Clock input of the 74F161. The buffer placed right next to 161 takes care to return this current in short loop to 161 GND if the clock is low.
As a buffer is pretty much mandatory, it is also used as clock selector. A crystal clock option (SRC419X asynchronous) is included.
The circuit outputs a fixed 8X (352.8/384kHz) DEM Clock (with the signal conditioning shown before), plus a WCK at BCK/32 and a BCK divided down from MCK. The BCK division can be selected as 8/4/2 for 1X, 2X & 4X sample rates.
If there is no intention to use a crystal clock or the crystal clock would be (say) fixed to something like 24.576MHz (for a fixed upconverted 192kHz Sample Rate on the TDA1541 and 6.144MHz as BCK) the circuit can be simplified by reclocking BCK from MCK and then dividing BCK by 2. Advantage here, we do not particularly worry about dividing MCK by the correct Ratio, as we use BCK to create our clock.
In this case DEM would need dividing by 64 from MCK. We will keep a 74F74 as final stage with differential Out, so divide by 32, so 74F161 & 1/2 74F74 or a 74HC4040 or similar.
The elaboration of this case is left to the reader.
Thor
Ok, in the above divider, we have a spare 74F74 section looking for a job.
The rate estimator in the SRC419X runs on LRCK and the reference clock. It has an LF corner of 0.00025*FS, or 48Hz for 192kHz sample rate.
Now, looking at the LRCK from something like XMOS we see as much as 1nS jitter and a lot is low in frequency.
If we want to (optionally) use the SRC function, we better reclock in the incoming LRCK into SRC419Xwith the source MCK.
Now input and output will have low jitter, so we do not rely on the ASRC to clean jitter, which is not great at.
Thor
I am moving all the different little snippets into a complete separate project.
If anyone want to contribute, let me know there. See you on the other side.
https://www.diyaudio.com/community/...ampling-dac-tda1541-throwback-project.426996/
Peace. Out.
Thor
If anyone want to contribute, let me know there. See you on the other side.
https://www.diyaudio.com/community/...ampling-dac-tda1541-throwback-project.426996/
Peace. Out.
Thor
So Thorsten's thread, above, has been banned by the moderators due to unfriendly comments within the thread.. What now? Will there ever be a new TDA1541A project? I speak only as a DIYer whose knowledge is a tiny fraction of others on this forum. However, I have built many successful projects from threads on DiyAudio and have a couple of single crown TDA1541A's waiting for a home.
I think everything important about the optimal implementation of this DAC chip has been written in this thread. Looking for a raw PCB including all "discoveries" is another question. I think @diyiggy has been working on it.
Some key point (I might have missed some):
- Stacked series voltage regulators à la Thor
- I2S signal conditioning
- BCLK reclocking to a low-jitter system clock
- DEM clock synchronized to BCLK or MCLK, 384 or 192 kHz
- Good quality DEM filter capacitors 100 nF to 220 nF, possibly larger at the MSB and MSB-1, MSB-2, ...
- Local decoupling at the three supply pins
- Careful separation of DGND and AGND
- Max. 33 ohms I/V resistor
- Optional: glitch adjustment (Nakamichi patent)
- Optional: sin(x)/x droop compensation in the analog stage
- Careful PCB ground planes (separate AGND and DGND) design, short tracks, etc.
The next level would be simultaneous mode, 2xTDA1541A in push-pull mode, and you still have a million options for the I/V conversion (resistor, R+transformer, opamp, R+tube, R+transformer+tube, transistor, FET, ...).