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Old 2nd June 2013, 10:25 PM   #4851
roger57 is offline roger57  Canada
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Hi oshifis,

Interesting...
What DEM circuit (pins 16, 17) have you implemented?



Quote:
Originally Posted by oshifis View Post
As for the 2x7 DEM filtering capacitors, I have been listening to the DAC with the capacitors removed altogether for a while. Same as with NOS, it shouldn't work, but it sounds impressive!
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Old 3rd June 2013, 07:55 AM   #4852
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by oshifis View Post
but it sounds impressive!
Hi, oshifis; what is it impressive?
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Old 3rd June 2013, 11:31 AM   #4853
oshifis is offline oshifis  Hungary
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I connected an 510 pF silver-mica capacitor between pin 16-17. This resulted in 176.4 kHz DEM oscillator frequency. I was hoping that the frequency will lock to 4x fWS, but for some reason it does not.
Apart from this, after removing the DEM filter capacitors, the sound is very realistic, life-like. It is worth trying, especially because it costs nothing.
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Old 3rd June 2013, 12:04 PM   #4854
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by oshifis View Post
I was hoping that the frequency will lock to 4x fWS, but for some reason it does not.
It needs a trimmer.
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Old 3rd June 2013, 01:16 PM   #4855
oshifis is offline oshifis  Hungary
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I tried tuning with an air trimmer, but it did not work either. I have an accurate frequency counter, and it was possible to tune the frequency to exactly 176.400 kHz. Then I checked the lock condition by triggering the oscilloscope externally with the WS signal, and checking the steps of the DEM switching on one decoupling pin (measuring the DEM frequency on the capacitor would de-tune the oscillator due to capacitive load). Ideally I should have seen clean synced 4-steps signal. I have seen a jittery smeared signal, instead. Also it is easy to de-tune the DEM oscillator by closing my hand to the capacitor.
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Old 3rd June 2013, 01:42 PM   #4856
SSerg is offline SSerg  Russian Federation
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Give on pin 16 (17) weakened clock 176.4 Khz. I was able in this way to get the synchronous operation of DEM.
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Old 3rd June 2013, 01:50 PM   #4857
oshifis is offline oshifis  Hungary
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Where can I get it from? I have only master clock and 44.1 kHz WS (using NOS, SAA7220 bypassed). I am afraid if I divide the master clock, it will introduce jitter. Should I use reclocking?
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Old 3rd June 2013, 01:55 PM   #4858
SSerg is offline SSerg  Russian Federation
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Jitter will be much less than in the case of free-generating DEM.
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Old 3rd June 2013, 02:44 PM   #4859
roger57 is offline roger57  Canada
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Have you tried ecDesigns solution of a 1000pf (1nF) capacitor to get an (approximate) 80KHz DEM clock? According to John, this results in adequate emitter tail currents being generated if 1uF decoupling caps are used. It seems that after reading the last 100 or so posts, "locking" isn't critical, at least according to ecdesigns. (or, please correct me if am wrong, John)

Right now, I have his original solution; using a 1.8nF capacitor. Since I implemented this last September, he has changed his mind on this value (he does do that after doing more research) and says the 1nF will be better.

I do find the sound right now to be a bit dark, but I've heard several theories on this, one being the 1uF are a bit large value for the decoupling - perhaps OK for the first 2 or 3 positions, but stick with 0.1uF/0.22uF for the others. I'm using the CD 1210 Acrylics. Can't find much info regarding a qualitative sound difference of this composition vs polypropylene, so perhaps that's a factor.

I first will try only changing the 1.8nF -> 1nF and see how that works out. If not, I may swap the higher decoupling caps -the top 3 - for 0.22uF.



Quote:
Originally Posted by oshifis View Post
I connected an 510 pF silver-mica capacitor between pin 16-17. This resulted in 176.4 kHz DEM oscillator frequency. I was hoping that the frequency will lock to 4x fWS, but for some reason it does not.
Apart from this, after removing the DEM filter capacitors, the sound is very realistic, life-like. It is worth trying, especially because it costs nothing.
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Old 3rd June 2013, 03:51 PM   #4860
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Hi oshifis,

Quote:
As for the 2x7 DEM filtering capacitors, I have been listening to the DAC with the capacitors removed altogether for a while. Same as with NOS, it shouldn't work, but it sounds impressive!
There can be a big difference between impressive and transparent sound. Impressive sound usually causes listening fatigue over time. Specific distortion can also sound impressive, one always has to be very careful not to mix-up impressive sounding distortion with transparent sound.

The DEM decoupling caps have a function, removing them can cause inconsistent performance (noise, low level distortion).

DEM decoupling is highly critical as GND noise and DC leakage currents can degrade performance.

Here is a possible solution, daisy-chain DEM decoupling (haven't tested this yet):

1uF cap between pins 7 & 8
1uF cap between pins 8 & 9
1uF cap between pins 9 & 10
1uF cap between pins 10 & 11
1uF cap between pins 11 & 12
1uF cap between pins 12 & 13
1uF cap between pin 13 & AGND (pin 5).

1uF cap between pins 24 & 23
1uF cap between pins 23 & 22
1uF cap between pins 22 & 21
1uF cap between pins 21 & 20
1uF cap between pins 20 & 19
1uF cap between pins 19 & 18
1uF cap between pin 18 & AGND (pin 5).

Decoupling values:

Bit 10, 143nF
Bit 11, 167nF
Bit 12, 200nF
Bit 13, 250nF
Bit 14, 333nF
Bit 15, 500nF
Bit 16, 1uF

Lowest bit decoupling still meets nominal value of 100nF. Injection of ground noise is greatly reduced, DC leakage current is greatly reduced.

It is also good practice to attenuate (switching) noise and mirror images (44K1, 88K2, 132K3, 176K4, 220K5 and so on) present at the DAC chip output.

I am currently experimenting with a 21 KHz Cauer-Pi low-pass filter with integrated 44K1 trap (parallel resonance circuit). Higher mirror frequencies will be handled by the low-pass function.

This filter is placed between DAC chip output and I/V stage input. The filter is loaded with approx. 13 Ohms (I/V stage input impedance). The Cauer filter is dimensioned such way that a trebles-boost is obtained by shaping the filter response.

This method can also be used with passive I/V conversion (I/V resistor on the DAC chip output), but the filter values have to be recalculated for the different load impedance (I/V resistor value).

here is an online calculator for Cauer Pi filters:

Chebyshev Pi LC Low Pass Filter Calculator

For 27 OHms I/V resistor (load impedance) for example one gets following values for 3 filter components: 289nF, 235uH, and 289nF.

It is important to use air core chokes.

The shunt capacitor value (44K1 trap) can be calculated with this LC series resonance calculator:

LC Resonance Frequency Calculator - Ekswai

The shunt capacitor for the 235uH choke would be 55.4nF.

The trap works as follows, at the tuning frequency of 44K1 the impedance of the parallel resonant circuit (235uH & 55.4nF) will rise significantly. This together with the relatively low load impedance (27 Ohms in the example) will result in extra attenuation of 44K1 (sample frequency).

One can verify filter operation by using a 1 KHz test signal, it should look perfectly smooth without any visible steps on the oscilloscope.

One could experiment with I/V resistor value so the filter can be built using (combinations of) standard E12 values for caps and choke.


Quote:
Ideally I should have seen clean synced 4-steps signal. I have seen a jittery smeared signal, instead.
When the DEM oscillator timing cap has the correct value there should be a lock, however, due to drift (temperature) lock-out can occur over time. The jitter is quite normal with the datasheet app, performance can be optimised by using an un-interrupted ground plane and very small (805 size) film cap with shortest possible traces.

Quote:
Also it is easy to de-tune the DEM oscillator by closing my hand to the capacitor.
EMI pick-up can be greatly reduced by the following:

6K8 between pins 15 & 16
6K8 between pins 15 & 17
Timing cap between pins 16 & 17 (value has to be increased due to reduced oscillator input impedance).

Attached picture of the DEM clock shows the typical DEM oscillator signal for this free running DEM clock.
Attached Images
File Type: jpg TDA1541A-MK17dem2.jpg (98.6 KB, 571 views)
File Type: jpg TDA1541A-MK17dem1.jpg (97.9 KB, 556 views)
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