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Old 12th April 2013, 08:28 AM   #4821
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Does it mean that the whole generation chain of I2S signals has to be CML / ECL?

I plan to do a balanced 2X TDA1543 NOS, needing to invert the data line of one of the TDA1543
any CML / ECL inverter buffer to do this?

I2S signals will come from a squeezebox or async USB receiver
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Old 12th April 2013, 10:27 AM   #4822
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Something like this?

https://picasaweb.google.com/lh/phot...eat=directlink

Though I don't know if the chips are CML/ECL or whatever...
I only follow instructions.

M.

Last edited by maxlorenz; 12th April 2013 at 10:30 AM.
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Old 12th April 2013, 02:09 PM   #4823
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I need something more simple, an inverter like 74ACT14 or 74ACT86 in CML / ECL

It has only to invert the polarity of the I2S data line
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Old 14th April 2013, 10:26 AM   #4824
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I am still pondering the ideal BCK supply to the tda...

Quote:
ECdesigns: Building the ultimate NOS DAC using TDA1541A

In the latest projects I use a high speed / low jitter divide-by-4 circuit running on 1.8V (1.8Vpp output signal). I feed this 1.8Vpp BCK signal to the TDA154x using only a 180R series resistor.
Quote:
ECdesigns: Building the ultimate NOS DAC using TDA1541A

BCK is extremely critical, attenuators are best avoided here, even plain series resistors are a problem (noise). Best results can be achieved by using 800mVpp BCK signal (not derived from an attenuator) with less than approx. 300 Femto seconds of jitter, but this is kind of "problematic"

So simply remove the BCK attenuator and hope for the best.
The ideal BCK trigger needs to be:
- jitter-'less', so as few components between the source and the tda.
- as low voltages as possible to avoid on-chip interaction.
- but minimum 1.8V to trigger
- difference between 'low' and 'high' must be at least 800mVpp.

So the ideal BCK signal would be between 1V and 1.8V.

My divide by 4 circuit consists of 2 74AUCG1 flipflops. I have a variable supply voltage to it, so I can fine tune the output of it. At this moment I have connected the flipflop directly to pin2 of the TDA.

The result of this is that the BCK signal is low at gnd, and high at 1.8V (I have test to go below 1.8V, and then it doesnt trigger the tda anymore, in line with john's findings.

So the likely thing to do would be to pull up the 'low' to 1V (or a bit less, like 0.9V) and leave the 'high' at 1.8V. Risk of course is injection of some additional supply noise into the signal, thereby increasing jitter....
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Old 15th April 2013, 07:11 AM   #4825
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Hi studiostevus,

Quote:
I am still pondering the ideal BCK supply to the tda…
Ideal BCK divider (divide-by-4) can be built using ECL (> 4 GHz). Signal swing would be 800 mVpp and typical jitter contribution would be 200 Femto Seconds.

When the bias voltage is corrected to 1.2V, the clock signal would then swing between +0.8V and +1.6V.

When using 74AU1G74 D flip-flops (typical 2.5ps jitter contribution for each D flip-flop) one could do following:

2.2V power supply (buffered 2.7V zener for example).
Anti-parallel 1N4148 diodes between Q output and BCK:

Q >| BCK
Q |< BCK

100R resistor between /Q output and BCK.

This would result in BCK signal swing between +0.6V (Q = "0" and /Q = "1") and + 1.6V (Q= "1" and /Q = "0").
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Old 15th April 2013, 10:05 AM   #4826
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Quote:
Originally Posted by -ecdesigns- View Post
Hi studiostevus,



Ideal BCK divider (divide-by-4) can be built using ECL (> 4 GHz). Signal swing would be 800 mVpp and typical jitter contribution would be 200 Femto Seconds.

When the bias voltage is corrected to 1.2V, the clock signal would then swing between +0.8V and +1.6V.

When using 74AU1G74 D flip-flops (typical 2.5ps jitter contribution for each D flip-flop) one could do following:

2.2V power supply (buffered 2.7V zener for example).
Anti-parallel 1N4148 diodes between Q output and BCK:

Q >| BCK
Q |< BCK

100R resistor between /Q output and BCK.

This would result in BCK signal swing between +0.6V (Q = "0" and /Q = "1") and + 1.6V (Q= "1" and /Q = "0").
Hi John, thanks for your note.

The 74au d flip flop solution is essentially the one you used a year ago in mk7 or so.

I am wondering whether using 2 diodes (jitter contribution) and a resistor (noise) to improve the ttl levels to reduce on-chip crosstalk, is a better solution than just leaving the ttl as is (Vlo=0v, Vhi=1.8v), having less jitter on the incoming bck signal and accepting the on-chip crosstalk....

Have you done any research on this perhaps?
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Old 16th April 2013, 01:54 PM   #4827
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In the meantime I tried the following:
74auc1g flipflop Q to pin2, and the power supply (1.8V) to the flipflop with series resistor 68R to pin2 as well. This lifts up the 'low' state to about 0.7V. So far seems stable and works fine.

Haven't yet properly compared to the situation without the pull-up resistor. Will do that tomorrow.
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Old 18th April 2013, 01:27 PM   #4828
SSerg is offline SSerg  Russian Federation
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Reading this article (http://www.unitest.com/theory/jitter.html),
I have come across on interesting picture.
Upper curve - a clock pulses (456 MHz), blue histogram - a histogram of the point of the transition.
The blue line - TIE (Time Interval Error – TIE), red line - a FFT for TIE that is to say the jitter spectrum.
Attached Images
File Type: jpg jitter spectrum.jpg (52.7 KB, 737 views)

Last edited by SSerg; 18th April 2013 at 01:45 PM.
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Old 27th April 2013, 05:42 PM   #4829
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Quote:
Originally Posted by Xpertv
Is it necessary to add 2mA to TDA1541 outputs while I\U is provided by OpAmp? (Stock variant like NE5532\LM833) Or this is only for resistor I\U?
-->
Quote:
Originally Posted by SSerg View Post
According to TDA1541 datasheet this is not required.
But if I/U is provided by opa-amp, accompaniment of 2 mA on output 1541 reduces the current through feedback resistor. This reduces the constant voltage on a opa-amp output (in ideal up to zero).
I have a nice Marantz DAC, TDA1541, and there we see separate 'channels' for the 2 mA bias current such that the I/V opamp is always at 0 volts, so no current feedback through the resistor; hence having an operating point with lowest distortion.
(apologies if I miss your point; Is this what you mean?)
albert
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Old 29th April 2013, 07:04 AM   #4830
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by triode_al View Post
Is this what you mean?
Yes. Giving 2 mA on the opamp input, we install the zero voltage on the opamp output. This minimizes distortions.
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