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Old 10th April 2013, 09:24 AM   #4811
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by marconi118 View Post
If this is true, what about TDA1545?
TDA1545 and TDA1543 vastly worse, than TDA1541(A). For TDA1545 THD is equal -88 dB at level of the signal 0 dB (-95 dB for TDA1541) and -35 dB at level of the signal -60 dB (-42 dB for TDA1541).
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Old 10th April 2013, 09:35 AM   #4812
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and comparing tda1543 to tda1545?

Ecdesign mentioned earlier that 1543 is better than 1541 for SD player, less internal jiiter
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Old 10th April 2013, 12:03 PM   #4813
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Quote:
Originally Posted by marconi118 View Post
and comparing tda1543 to tda1545?
THD for TDA1543: -75 dB and -30 dB for signal level 0 dB and -60 dB accordingly. Else worse, than at TDA1545.

Quote:
Originally Posted by marconi118 View Post
Ecdesign mentioned earlier that 1543 is better than 1541 for SD player, less internal jiiter
I can't agree with this opinion. It is deeply wrongly.
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Old 10th April 2013, 02:25 PM   #4814
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Quote:
Originally Posted by marconi118 View Post
If this is true, what about TDA1545?

Should have an even better sound than 1543 without the DEM clock problems?
I've found that TDA1545A does sound better than 1543 but only when the output is carefully filtered to reduce the glitching. Being a CMOS chip it generates a substantial quantity of switching noise on its PSU. If the impact of this HF noise on the following circuitry isn't minimized, it sounds more gritty than 1543 despite posting better specs.
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Old 11th April 2013, 07:58 AM   #4815
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Hi marconi118,

Quote:
with state of the art applications with high time resolution it has many advantages to use a TDA1543

If this is true, what about TDA1545?
The SDV1-player was specifically designed to obtain highest possible time resolution with currently available (and affordable) parts. Feedback from audiophiles suggests that this is a -highly- desirable feature in digital audio sources.

Note that just using a TDA1543 in an application is meaningless without providing the environment required for obtaining highest possible time resolution.

TDA1545 is based on noisy CMOS logic (4mA supply current) and the continuous calibration causes similar problems like with DEM. So it is unusable for obtaining high time resolution.

The reason why I am no longer using ultra high speed CMOS circuits for clock, clock distribution, and DAC chip is that these have approx. 12.5 times higher jitter contribution compared to CML / ECL.

Typical jitter contribution of an ultra high speed CMOS (275 MHz): 2.5ps
Typical jitter contribution of CML / ECL (4 GHz): 0.2ps

The reduction of approx. 2.5ps to 0.2 ps is -very- clearly audible with NOS that is -least- sensitive to jitter.

The jitter spectrum is alo of greatest importance for perceived sound quality. So when jitter amplitude has reached its practical limits, further improvements can be made by tuning the residual jitter spectrum.
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Old 11th April 2013, 08:11 AM   #4816
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Afaik the main jitter bottleneck for ECLs was the ECL-TTL conversion which was worse than going with TTL all the way.
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Old 11th April 2013, 09:22 AM   #4817
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Quote:
Originally Posted by -ecdesigns- View Post
So when jitter amplitude has reached its practical limits, further improvements can be made by tuning the residual jitter spectrum.
Hi, -ecdesigns-

How you offer to adjust the jitter spectrum?
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Old 11th April 2013, 11:32 AM   #4818
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Hi s3tup,

Quote:
Afaik the main jitter bottleneck for ECLs was the ECL-TTL conversion which was worse than going with TTL all the way.
True, one ECL to TTL translator would contribute approx. 2.5ps of jitter. This would equal the jitter contribution of a single ultra high speed CMOS gate.

But why convert ECL to TTL when using TDA154x DAC chips that are already based on Current Mode Logic with typical 400mVpp signal swing?

ECL can drive TDA154x chips perfectly while providing very low jitter contribution.
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Old 11th April 2013, 12:40 PM   #4819
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Hi SSerg,

Quote:
How you offer to adjust the jitter spectrum?
I use an electronic tuning fork. Phase noise spectrum tuning is mainly obtained by tuning the properties of the active single transistor drive circuit.

First oscillogram shows the drive signal (input node, 0.5V/div, 11.289 MHz).
Second oscillogram shows the signal on the primary node (1V/div, 11.289 MHz).
Third oscillogram shows the signal on the secondary node (1V/div, 11.289 MHz).

All 3 nodes are "isolated" for all frequencies but the fundamental (11.289 MHz). This prevents cross-pollution between connected circuits.

The microcontroller is connected to the primary node using a low pass fliter / attenuator
The PECL divider is connected to the secondary node.

PECL divider circuit outputs 800mVpp BCK signal with exactly 1.1V DC bias.
Attached Images
File Type: jpg drive signal.jpg (94.1 KB, 671 views)
File Type: jpg primary node.jpg (90.7 KB, 546 views)
File Type: jpg secondary node.jpg (95.2 KB, 531 views)

Last edited by -ecdesigns-; 11th April 2013 at 12:45 PM.
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Old 12th April 2013, 07:13 AM   #4820
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ah.. ok, so BCK does get biased up to 1.x VDC even though it receives no attenuation as per the previous questions/comments about 3.3V I2S feed.
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