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Old 25th February 2013, 11:44 PM   #4741
Eldam is offline Eldam  France
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@ Andrea : thank you for the formule and the experience. So if we need to trigger, do we need a scope or is it possible with the ears like the Weber carburators of a Giuletta (no buzzzz in the speaker ? Sorry for the naive question!) ? Do you need to stay with the air trigger cap after finfing the good value or does exist a cap with the exact value (or very near) ?

@Crobbins : not surprised here : ok long legs but the good result of the Polypropylen ! The Wima or MKT I tried sounded very dry in my systems, 1 uF Bck ceramic too like John explained (resonances)... When I will make the DAC I will do a match between Polypro, Polysulfid, Polystyren and solid tantal ("+ leg" to Gnd) and the 2 refs John 's SM cap. It's DIY for me and i have already some big caps here
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Old 26th February 2013, 04:54 AM   #4742
oshifis is offline oshifis  Hungary
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Quote:
Originally Posted by andrea_mori View Post
The resistance of TDA1541 DEM RC oscillator should be around 1K85, so you can calculate the capacitor value for any frequency using the typical RC oscillator formula: c = 1 / (2 * Pi * 1850 * fDEM) (capacitance in Farad). Around 485 pF for 176kHz. BTW, I believe the resultant capacitor value has to be trimmed to lock (thanks James).
There could be also some tolerances from batch to batch. E.g. I measured f = 12.000 kHz with C = 7500 pF, and from this I calculated R = 1.768 kohm and C = 510 pF for 176.4 kHz on my test setup. Another chip might have slightly different R, so it seems a variable capacitor for achieving the locking condition can't be avoided.
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Old 26th February 2013, 08:51 AM   #4743
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Yes, the internal R value has a tolerance, maybe it could vary within the same batch. That's the reason to use a variable cap in parallel with the fixed cap to fine tuning the lock condition. I have not yet tried, but seems the good practice was tuning the lock condition using a low level recording, ecdesigns, chris and james could explain how to do that.
Maybe, the best solution could be using a variable cap to determine the exact total cap value, measuring the total capacitance of both caps after tuning, then replace both with a fixed capacitor with the right value, that's means get the right capacitor from a big bag of them. I don't know how the final value is critical, a few pF or less, maybe someone could share his experience.

Anyone did try to sync the DEM clock at 88K2, starting with the WS signal followed by a frequency doubler? Strange idea, maybe someone could give a try.
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Old 1st March 2013, 11:54 AM   #4744
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by oshifis View Post
I would be also interested in jitter measuring techniques in general.
Hi, oshifis, here is article.
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File Type: pdf Specifying_Jitter_Performance.pdf (451.3 KB, 136 views)
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Old 1st March 2013, 09:42 PM   #4745
Eldam is offline Eldam  France
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hi,

For DEM clock oscilator between with pin 1 (WS) and pin 16 : must we use 330 nF + 22K in serie ?
Please, Is there a method to lock with air cap trimer with ears (using speakers) or do we have to use a scope ? (no go for me)
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Old 2nd March 2013, 07:17 PM   #4746
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Quote:
Originally Posted by Eldam View Post
Please, Is there a method to lock with air cap trimer with ears (using speakers) or do we have to use a scope ? (no go for me)
You can play low volume music (-40db or lower). Once the dem oscillator locks, you will hear the music clearly. If it's not locked, you will hear digital noise.
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Old 3rd March 2013, 03:01 PM   #4747
Eldam is offline Eldam  France
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Thank you Studio Stevus,

Because i will use the same source as you (SB receiver, if you have the opportunity to check one day the value of your 3 resistors in your I2S attenuation, it will be a pleasure to read you again...)

Super, I can beginn, i read, re-read and sometimes read again this post and I try to go with the last version with WS Soft DEM. So I have all but the I/V and the clock now. For the clock it's not a problem, I try to do the last version that ECdesigns (John) described or go to a kwak or Tentlab...

With OS and several cd players (TDA1541a or TDA 1540D) a too high value (>1uF) decoupling cap sound dry and harsch but this is OS and without change the running free sync Clock cap. 470nFdecoupling cap with the first 2 pins works fine for me with these two chips like the Philips LHH2000 but this is OS.

I don't understand the exact sound interaction between MSB decoupling cap & the sync clock cap in NOS mod... The higher the MSB, the Higher the clock cap = soft sound ? SSerg give me a doubt about the frequency and nobody report (but John) with the best match between frequency & MSB value. I surmise the proof of concept depends of the quality of the I/V stage and the rest of the hifi system...maybe and the quality of the cap surely!

I have to go to NOS now with this project and start with 1 uF Cornel Dublier SM cap first and will benchmark others caps when this project will make a sound (i hope!).

SO the I/V stage will be another story. Ihave a 100k input with my amplifier. But this chip is 30 years old and everybody is still talking about the ideal shematic after the tda1541... Gomez seems good even with modern tubes (Siemens D3A for 1st stage & ? for second). It seems a discrete can be good enough but this is the war here with NTD1, Cen, Zen, jocko,... I have to try but many times and money !
But it's a hobby, so thank you all for the advises and shematics, especially John here. I hope John comes back with new benchmarks with i/v stages.

cheers

Last edited by Eldam; 3rd March 2013 at 03:16 PM.
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Old 5th March 2013, 01:46 AM   #4748
Ceglar is offline Ceglar  Australia
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Default Clarification on Attenuators with 3.3V source (incl. BCK)

Hi ECdesign and others,

Quote:
crobbins5421 writes -"So for 3.3V application, BCK attenuation stays about the same with 5x 100R resistors, inductor, 220R pull-up, 68R pull down?..."

ecdesigns replies "In the latest projects I use a high speed / low jitter divide-by-4 circuit running on 1.8V (1.8Vpp output signal). I feed this 1.8Vpp BCK signal to the TDA154x using only a 180R series resistor.
I'd like to ask what should ideally be done with BCK when its fed from a 3.3V source.

I can see that its amplitude will be about twice the level of WS and DATA (~1.7Vpp) when WS and DATA are using the 1k series and 1k + 680 voltage divider across the 3v3 supply.

From 3v3, (20 DCR inductor + 150R) +(100R) voltage divider would draw (3.3/270) = ~12mA and bias the input at ~1.2V when connected at the top of the 100R pull down resistor.

Is it then a simple matter of using 100R series resistor between the 3v3 BCK source and the top of that 100R pull down resistor (BCK/2) to reduce 3v3 BCK to ~1.65Vpp?

Is it close enough to be ok, or something else?.. (more series R, higher value pull down, higher value pull up, less current, same bias voltage, more attenuation ?)


Thanks,
Shane

Last edited by Ceglar; 5th March 2013 at 01:47 AM. Reason: title.
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Old 5th March 2013, 06:04 AM   #4749
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Since they are wideband digital signals, they should be handled in very particular way to conform digital signal transmission techniques such as impedance matching.
Your "divider" is basicly an attenuator which output impedance should be matched to the characteristic impedance of the trace (cable) you feed it thru, as long as it is being placed on the source of transmission line. It's source impedance is easily calculated of paraleling these 3 resistors.

Another way of dropping-off the level of signal is to terminate it in series at the source's end, make attenuator's input impedance the same as incoming transmission line, and source impedance the same as outgoing transmission line impedance... Much over my head i'd think, especially when you have to bias the output HI/LO voltages at particular level
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Old 6th March 2013, 05:25 AM   #4750
Ceglar is offline Ceglar  Australia
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Quote:
Originally Posted by s3tup View Post
Your "divider" is basicly an attenuator which output impedance should be matched to the characteristic impedance of the trace (cable) you feed it thru, as long as it is being placed on the source of transmission line. It's source impedance is easily calculated of paraleling these 3 resistors.
Thanks for this..

I'm a little confused because if the source impedance is the parallel value of the three resistors, consider the values of both WS and DATA 3k3//3k3//1k = 622ohms in the 5V attenuator cct, and 1k//1k//680 = 288 ohm in the 3v3 attenuator cct.

However, the values for WS and DATA have been given, and just BCK remains unknown (to me anyway). If I use the given values for the 5V cct 500//68//220 = ~47ohms.

If the attenuation is a function of the voltage divider created by the series resistor and the shunt resistor to ground, then signal level for WS and DATA in the 5V cct, after the divider, is 1.1V (this is Vpp?) and only 0.59V for BCK?.

If its desirable to have amplitude of the three lines between 1.2 and 1.4Vpp, and each biased between 1 and 1.4V, with a parallel resistor value of ~50 ohms for BCK, then the values I've arrived at are as in the attached image.

Does this all seem correct, or at least correct enough for the purpose, or have I got it all backwards?

Thanks,
Shane
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File Type: jpg I2S.jpg (102.9 KB, 517 views)
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