Building the ultimate NOS DAC using TDA1541A

[oshifis]

Originally Posted by SSerg

And...? What further? What shall give us the external resistor?

That is an unvanted parasitic resistor due to leakage, not a real component. The less the leakage the better, ideally this resistor is infinite. Also it has influence on the actual bit current only (B16 to B10). The DEM cell sets the very exact bit current ratio 2:1:1. But this external leakege "diverts" a part of the precisely set bit current before summing to the analog output.

[SSerg]

Hi, oshifis!

Originally Posted by oshifis

That is an unvanted parasitic resistor due to leakage, not a real component. The less the leakage the better...

This it clear, colleague. Incomprehensibly, why you want to connect the external resistor towards filtering capacitor. You this offers, not so?For simulation or with the other purpose? For simulation it is enough will draw him on paper. And not it is important, is connected he towards capacitor from outside or from the inside of microcircuits.

[SSerg]

With troding cristmas, friends!

[maxlorenz]

I wish happy festivities to everybody.

M

PS: I received this email few days ago; "as far as things are going, I am not so concerned by the arrival of the End of the World but by the arrival of the end of the month"

[jstang]

I use the native 48 bit cdpro i2s. Which ends up being clocked slower for 44.1k. You can change the cdpro to use other formats, but slower is better to reduce digital noise.

Jk

Originally Posted by andrea_mori

Just a doubt about clock distribution (8.4672 master clock, CD PRO and TDA1541 NOS mode): 8.4672 MHz (inverted/inverted) directly to CD PRO clock, master clock divided by 4 (flip-flop), so 2.1168 MHz, to DAC bck...
data and WS directly from CD PRO I2S to DAC?
or just reclocked by flip-flop?

One more question: replacing CD PRO with QA-550 sd card player is that correct the above configuration?
The QA-550 use an 11.2896 MHz clock, can I assume it outputs 2 words of 32 bit at fs, so bck is 2.8224 MHz (11.2896 divided by 4)?

Thanks
Andrea

[jstang]

Oh and everything is reclocked by a low jitter clock prior to being used by 1541s 4x s1. The on board cdpro clock is not worth using. Use the low jitter clock source for the cdpro and to reclock the i2s.

Jk

Originally Posted by jstang

I use the native 48 bit cdpro i2s. Which ends up being clocked slower for 44.1k. You can change the cdpro to use other formats, but slower is better to reduce digital noise.

Jk

[wlowes]

Originally Posted by SSerg

Hi, oshifis,
You are right. Towards quality of the capacitor insulation and of the PSB insulation are presented serious requirements. (You about this did not know earlier?) I will say more. Hard requirements are presented towards quality of the gumboil too. His remainder must not be conducting.

It strikes me that the optimal way to use the 1541a may be by point to point wiring. We are using pt to pt with the smt caps mounted on the pins. DEM circuit is more or less the same. I mount filtering caps on the pins of power supplies. All that is left is I2s and output. Why muddy the water with PCB? Most of these pins are just used to anchor the device. Would it not be better to use a pcb that has most of the chip floating in the air?

[dacen]

For those of you that are into CD-PRO2, this might be an interesting link :

Bergrans CD-Pro2M controller :: Home

[qusp]

Originally Posted by wlowes

It strikes me that the optimal way to use the 1541a may be by point to point wiring. We are using pt to pt with the smt caps mounted on the pins. DEM circuit is more or less the same. I mount filtering caps on the pins of power supplies. All that is left is I2s and output. Why muddy the water with PCB? Most of these pins are just used to anchor the device. Would it not be better to use a pcb that has most of the chip floating in the air?

because if done properly, having a ground plane for decoupling VHF signals does the opposite of muddying the waters. You still need to think of how the currents flow in the ground plane/s for best results, but if you decouple right on the pins with SMD parts, but the nearest low impedance ground is not local (for example connected by a wire), then you havent really done much good IMO and have wasted the low inductance of the parts.

Parasitic leakage will find a way even without a PCB, without a PCB and ground, EMC noise from the i2s and clock signals will have a whale of a time jumping all over the place. depending on speeds they dont even need a conductor to travel on.

[studiostevus]

Originally Posted by qusp

because if done properly, having a ground plane for decoupling VHF signals does the opposite of muddying the waters. You still need to think of how the currents flow in the ground plane/s for best results, but if you decouple right on the pins with SMD parts, but the nearest low impedance ground is not local (for example connected by a wire), then you havent really done much good IMO and have wasted the low inductance of the parts.

Parasitic leakage will find a way even without a PCB, without a PCB and ground, EMC noise from the i2s and clock signals will have a whale of a time jumping all over the place. depending on speeds they dont even need a conductor to travel on.

thinking of your comment makes me doubt my latest revision of my pcb... I am packing the tda, reclock circuit, masterclock and four salas regulators on a double sided pcb. The bottom plane is a single ground plane (largely uninterrupted), carrying:
- analog signal gnd
- digital signal gnd, including some 11mhz masterclock and 2.8mhz bck
- psu gnd
- tda filter cap currents

The layout is such that :
- the salas regulators are on the right side of the tda. I am hoping that keeps the psu gnd currents to this side of the pcb.
- the analog signal is routed off the board immediately (to external i/v and tube stage)
- the digital signals are located on the left side of the pcb, so I am hoping that keeps gnd currents in this area as well.
- it would seem logical that the currents coming from the tda filter caps (decoupling caps) would stay under the tda, even if a single gnd plane is used instead of a pcb trace to route these back to agnd. Can someone confirm?

Has my thinking on currents been too simplistic? My previous design used 2 gnd planes (top and bottom) for agnd and dgnd.