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Old 24th November 2012, 06:28 PM   #4641
ash_dac is offline ash_dac  United Kingdom
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Quote:
Originally Posted by oshifis View Post
Moving average ~ low pass filtering
The internal resistance of the bit current generator and the external capacitor does exactly this. This arrangement simply can't take 4 DEM periods, average them (how? calculating the mathematical average?), take the next 4 DEM periods, do the same, etc. The only important thing is to have a precise 50% duty cycle of the DEM clock - as the cited article states. John also concluded that it can be best achived by decreasing the DEM frequency (and increasing the external capacitor at the same time).
The technical papers I read referred to at low DEM fs you would need very large impractical cap' values on the decoupling pins to filter the ripple. Though the paper also discussed an option using the same clock fs for all stages in the divider and the timing error. The tda1541a datasheet uses all 100nf I believe. ECDesigns directed me to Td1540 datasheet where they show a divide by 2 on the decoupling caps. I don't know if the tda 1541a is the same but it might just be the practical implementation.

That said I am coming to the conclusion that it isn't possible to push the DEM fs higher after reading ECDesigns, and other posters.

Arcam in their black box did tinker running a 680pf oscillator, and varying the decoupling caps. They also ran the tda1541a at -6.2V....

I must get my black box out of storage. edit: It did not sound that great to be honest.

Arcam Delta Black Box1 mods

Last edited by ash_dac; 24th November 2012 at 06:30 PM.
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Old 25th November 2012, 01:24 PM   #4642
wlowes is offline wlowes  Canada
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Default arcam mods

Quote:
Originally Posted by ash_dac View Post
I must get my black box out of storage. edit: It did not sound that great to be honest.
ash_dac
In case you did not see it, there is a very good record of mods made to arcam alpha at
Arcam Alpha mods
Schematic of black box and alpha have many similarities. Shame to have black box in storage.
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Old 25th November 2012, 02:19 PM   #4643
oshifis is offline oshifis  Hungary
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Quote:
Originally Posted by -ecdesigns- View Post
Voltage measurement suggests following active divider output to decoupling pin assignment:

Bit 16 (MSB) pins 12 & 23, bit15 pins 13 & 24, bit14, pins 11 & 22, bit13, pins 10 & 21, bit12, pins 9 & 20, bit11, pins 8 & 19, bit10, pins 7 & 18.
I just measured the voltages at the DEM pins:

Pin 13, 18, 12, 19: -7.4 ... -7.6 V
Pin 11, 20, 10, 21: -5.2 ... -5.5 V
Pin 9, 22, 8, 23: -3.9 V
Pin 7, 24: - 3.5 V

Based on the diagram of the DEM switch principle I conclude in the following pin assignment:

Bit 16 - pins 13, 18
Bit 15 - pins 12, 19
Bit 14 - pins 11, 20
Bit 13 - pins 10, 21
Bit 12 - pins 9, 22
Bit 11 - pins 8, 23
To passive divider (Bits 10 to 1) - pins 7, 24

I also measured the ripple at each pins by removing the external capacitors (using C = 1.5 nF resulting in fDEM = 60 kHz). Each pin showed a four step pattern repeating, the length of each step was one DEM sample.
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Old 26th November 2012, 12:54 PM   #4644
SSerg is offline SSerg  Russian Federation
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Hi, -ecdesigns-

Quote:
Originally Posted by -ecdesigns- View Post
- TDA1541A typical application runs in 4 times oversampling.
At given thread we discuss working of 1541 without oversampling (NOS). Work with oversampling a separate subject.
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Old 26th November 2012, 01:03 PM   #4645
SSerg is offline SSerg  Russian Federation
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Hi, studiostevus

Quote:
Originally Posted by studiostevus View Post
I could be certainly way off here, as i am by no means an expert, but i still don't see how a 22khz dem clock (fDEM = 2fWS when using no oversampling) would give a satisfactory result.... If anyone can explain where my understanding is flawed?
Why fDEM = 2fWS? fDEM = 0,5fWS!

Apropos, in
TDA1541 no resistor, which it is necessary to adjust. You unattentive read the article.
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Old 26th November 2012, 01:06 PM   #4646
SSerg is offline SSerg  Russian Federation
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Hi, brubeck,

Quote:
Originally Posted by brubeck View Post
I tend to share your thoughts, but the size of the external capacitor plays also a role i suppose. If it has higher capacitance, it will act like a voltage buffer and equalizes the (DEM) ripple to a moving average voltage? Viewed that way i can imagine that lower fDEM doesn't much affect the results of DEM. Then it is not related to 1 word, but time moving average.
You not rule. DEM averages DC constituting of bit current. The capacitor filters AC constituting of this current, but he can not average DC constituting because capacitor at direct currents does not operate. So capacitor can not operate instead of DEM.
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Old 26th November 2012, 01:10 PM   #4647
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by oshifis View Post
I just measured the voltages at the DEM pins:

Pin 13, 18, 12, 19: -7.4 ... -7.6 V
Pin 11, 20, 10, 21: -5.2 ... -5.5 V
Pin 9, 22, 8, 23: -3.9 V
Pin 7, 24: - 3.5 V

Based on the diagram of the DEM switch principle I conclude in the following pin assignment:
Bit 16 - pins 13, 18
Bit 15 - pins 12, 19
Bit 14 - pins 11, 20
Bit 13 - pins 10, 21
Bit 12 - pins 9, 22
Bit 11 - pins 8, 23
To passive divider (Bits 10 to 1) - pins 7, 24
You rule, oshifis.

Here is table of my measurements, as well as my reconstruction of the internal scheme of TDA1541.
Attached Files
File Type: pdf Напряжения на в.pdf (66.8 KB, 162 views)
File Type: pdf TDA1541A_реконструкци.pdf (204.9 KB, 179 views)
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Old 26th November 2012, 01:37 PM   #4648
oshifis is offline oshifis  Hungary
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Very interesting measurements. But my measurement and the analysis of the DEM circuit operation shows pulse width = 1 / fDEM on all pins. A pattern of four such pulses each having slightly different amplitude repeats itself. Does Частота пульсаций mean the ripple frequency? Did you measure it, or theoretically concluded?
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Old 26th November 2012, 01:47 PM   #4649
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by oshifis View Post
Does Частота пульсаций mean the ripple frequency?
Yes.

Quote:
Originally Posted by oshifis View Post
Did you measure it, or theoretically concluded?
Theoretically.
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Old 27th November 2012, 07:33 AM   #4650
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Hi oshifis,

Quote:
But my measurement and the analysis of the DEM circuit operation shows pulse width = 1 / fDEM on all pins.
I also measured same ripple frequency on all active divider outputs with decoupling cap removed.

Article about DEM circuit shows two different frequencies as SSerg indicated.

f for single active divider output and f/2 for paralleled active divider outputs.

f/2 occurs in theory when a specific combination of tolerances is present on both paralleled outputs. I never measured this in practice, and I measured many TDA1541A chips.

After filtering, the ripple current should be so low that it has no audible effect at all (far less than 1 LSB).

When jitter on the DEM oscillator is -not- random, it can lead to slowly fluctuating bit current errors on the active divider outputs. These cannot be filtered out by the decoupling cap as it wasn't dimensioned to attenuate ripple frequencies that are much lower than fDEM.

Example, when the DEM frequency is phase modulated with a sine wave of say 50Hz (mains) it translates in a specific distribution of interval timing that in turn results in bit errors that vary with 50Hz pattern. In other words, a low frequency ripple current is generated by DEM oscillator phase modulation. The decoupling caps (100nF typically) are not able to attenuate these low frequencies as they were dimensioned to filter out 150 250 KHz ripple only. This would be periodic jitter.

Instead of 50, 60, 100, 120 Hz phase modulation as a result of power supply ripple for example, the DEM oscillator can also be phase modulated by low frequency components (that have too low frequency to be filtered out by the decoupling caps) generated by DATA or L-OUT and R-OUT. This would be deterministic DEM oscillator jitter.

This non-random phase modulation of the DEM oscillator leads to slowly fluctuating bit errors that become audible as the decoupling caps fail to attenuate this low frequency ripple.
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