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Old 13th November 2012, 11:35 AM   #4611
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I must admit that I'm quite a bit puzzled by the idea of reducing the "DEM clock" freq down to 60Hz, with no other sinc pulse/clock involvement, but it's simple enough to try out and see what happens with my "much abused" old player .....

This dac chip continues to amaze, and I'm really pleased with the sound of Patrick's CEN o/p stage.
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Old 13th November 2012, 06:04 PM   #4612
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Hi tessier,

Quote:
Your I2S attenuators are designed for 5V TTL levels.
DATA and WS attenuators are designed for 3V3 signals (SD8-transport also outputs 3V3 signals).

Quote:
Can you tell me the value of your I2S attenuators resistors for a 3.3V I2S ?
For WS and DATA:

1K series resistor between digital audio source and TDA1541A I2S input.
680 Ohm pull-down resistor between TDA1541A I2S input and GND.
1K pull up resistor between TDA1541A I2S input and 3V3 (use digital audio source power supply).
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Old 13th November 2012, 06:37 PM   #4613
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Hi studiostevus,

Quote:
Although I am by no means an expert, I would think that although the DEM system can be viewed as a separate module (as can be seen indeed in the tda1541a internal schematic), spikes would nevertheless find their way to the substrate.
On-chip crosstalk cannot be avoided, but it can be lowered by reducing DEM oscillator frequency. Synchronising or triggering the DEM oscillator is possible (44.1 KHz with 2uF decoupling caps or 88.2 KHz with 1uF decoupling caps) but extra interference would be injected into the chip causing more problems. It is also essential that the free running DEM oscillator has low jitter, this cannot be guaranteed by the data sheet application (DEM timing cap pins 16 & 17 pick-up noise that then translates to jitter).

In order to get highest performance with the TDA1541A it is essential to minimise on-chip jitter by tuning external circuits.

Quote:
Nevertheless, I would still be interested to understand the current views vs. earlier assumptions related to substrate bounce etc…
I already applied I2S attenuators in earlier designs. I2S attenuators reduce signal amplitude, this reduces on-chip ground-bounce and related on-chip jitter.

Ground-bounce can also be lowered by reducing frequency. What's new is I2S signal band limiting that reduces the maximum fundamental frequency entering the DAC chip to approx. 2.8224 MHz.

Other cause for on-chip jitter is trigger uncertainty. Trigger uncertainty can be reduced by using cleanest possible supply voltages for both, -5V and +5V.

+5V supply ripple can be reduced to absolute minimum value by routing all bit currents back to +5V. Failing to do so will result in ripple on the +5V that relates to music content, causing on-chip deterministic jitter.

I/V circuits that result in relatively high on-chip deterministic jitter are:

- Low value I/V resistor between DAC output and GND.
- Diamond buffers.
- Op-amps.

These route selected bit currents to GND while unselected bit currents are internally routed to +5V.
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Old 14th November 2012, 07:20 AM   #4614
JOSI1 is offline JOSI1  Germany
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Hello John,

Quote:
Originally Posted by -ecdesigns- View Post
Hi studiostevus,

It is also essential that the free running DEM oscillator has low jitter, this cannot be guaranteed by the data sheet application (DEM timing cap pins 16 & 17 pick-up noise that then translates to jitter).

.
Can I reduce this problem by disconnecting pins16/17 from the PCB and solder the timing cap (e.g. 1nF NPO 0603) directly to the IC pins 16/17.
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Old 14th November 2012, 08:04 PM   #4615
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Hi Jameshillj,

Quote:
I must admit that I'm quite a bit puzzled by the idea of reducing the "DEM clock" freq down to 60Hz
It's 60 KHz with 1uF decoupling caps. Typical DEM clock is 150KHz ... 250KHz with 100nF decoupling caps. By increasing decoupling cap value I can lower the DEM frequency while maintaining low ripple on the active divider outputs.

Today I tested 22KHz DEM frequency in combination with 2uF SMD film decoupling caps, (two stacked 1210 size caps on their side just fit underneath the TDA1541A and provide 1206 footprint). Seems lower DEM frequency is better, provided decoupling caps have large enough value for effective ripple attenuation.
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Old 14th November 2012, 09:29 PM   #4616
ash_dac is offline ash_dac  United Kingdom
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Is 60Khz the lowest you can go? I remember there was someting about a divide by 2 in the thread / dem circuit notes so I guess that would still be frequencies outside of the audio band. In addition I suppose the cap size would also increase to much larger levels which bring their own problems!

Is there any merit to using higher value caps on different pins? I think a few commercial manufacturers did this ? (there is a thread on it I think )
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Old 15th November 2012, 09:16 AM   #4617
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Hi ash_dac,

Quote:
Is 60Khz the lowest you can go?
I am now using 22KHz (post # 4615). This is the lowest practical value, just outside the audio range and small SMD 2uF decoupling caps can be constructed by placing two 1uF 1210 size film caps in parallel. These will just fit under the IC when the IC is placed in an IC socket.

Quote:
In addition I suppose the cap size would also increase to much larger levels which bring their own problems!
They would likely have much higher inductance (poorer ripple attenuation). Short PCB traces that connect the decoupling cap are already problematic. That's why the decoupling caps are best placed underneath the chip, as close to the decoupling pins and GND as possible. Electrolytic caps have both, too high inductance and too high leakage current. Note that plus of electrolytic decoupling caps would go to GND.

Quote:
I remember there was someting about a divide by 2 in the thread / dem circuit notes so I guess that would still be frequencies outside of the audio band.
Since pins 16 and 17 are both inputs and outputs it is difficult to trigger / sync the circuit by external signal(s) without inducing peak currents. These peak currents increase on-chip interference and resulting jitter levels.

Quote:
Is there any merit to using higher value caps on different pins? I think a few commercial manufacturers did this ? (there is a thread on it I think )
I attached TDA1541A DEM block diagram.

Ripple current is reduced on each subsequent active divider output as a result of current division. So Highest ripple current is present on bit 16 (MSB) and lowest on active divider output that feeds the 10 bit passive current divider. Ripple current also depends on tolerances in the passive divider that is part of each active divider.

Logically speaking we could halve the decoupling cap value on each subsequent active divider output. With 2uF on bit 16 we could have 1uF, 470nF, 220nF, 100nF, 47nF, and 22nF on the following active divider outputs. Something similar was already indicated in the TDA1540 data sheet:

TDA1540 datasheet pdf datenblatt - List of Unclassifed Manufacturers - 14-Bit DAC (Serial Output) ::: ALLDATASHEET :::

Also interesting to see that 10nF seems to be lowest practical value, as subsequent bits all have 10nF caps installed.

Voltage measurement suggests following active divider output to decoupling pin assignment:

Bit 16 (MSB) pins 12 & 23, bit15 pins 13 & 24, bit14, pins 11 & 22, bit13, pins 10 & 21, bit12, pins 9 & 20, bit11, pins 8 & 19, bit10, pins 7 & 18.

Listening tests however showed that equal value DEM decoupling caps offer darker background and better detail.
Attached Images
File Type: jpg TDA1541ADEM.jpg (86.7 KB, 863 views)
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Old 15th November 2012, 07:51 PM   #4618
ash_dac is offline ash_dac  United Kingdom
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Thanks, really interesting.Though I think I'm confused as I have in my head the lowest frequency and current ripple to filter on the LSB? I think I might have the circuit the wrong way round in my head!

Again appologies for the lack of understanding.
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Old 19th November 2012, 04:34 PM   #4619
koldby is offline koldby  Denmark
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-ecdesigns-
How do you impliment using 22 Khz ?

Do you use a cap between 16 and 17?
How big?
And what does the DEM sync. look like?

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Old 21st November 2012, 08:05 AM   #4620
SSerg is offline SSerg  Russian Federation
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Hi, oshifis
Quote:
Originally Posted by oshifis View Post
I call this a negative attitude. A more positive attitude would be something like this:
"Look, I don't like your solution for this and this reason. It can be done better. Here is the circuit diagram, photograph, and some measurements from the prototype of my solution - which I can demonstrate is better than your approach"

You are rule colleague. Offered by you approach
is a constructive approach if prototype is discussed. But if they are discussed mathematical calculation or technical features, there is no need to build and present the prototype. It is enough to point to mistake, inexactness at calculation to insure others from repetition of the mistake.
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