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Old 11th November 2012, 03:41 PM   #4601
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Join Date: May 2006
Location: Holland
Hi studiostevus,

Quote:
John, fDEM of 60KHz? What brought along this odd frequency? Not a multiple of either ws or bck….
DEM clock frequency does not need to be equal to or a multiple of WS nor BCK. The DEM system can be viewed as a separate module that simply provides binary weighted DC bit currents for each channel.

The reasons I abandoned DEM oscillator synchronization are increased on-chip interference levels and the extra clock load on the super critical clock signals.

Two factors are most important:

1) DEM switch settling time.
2) Effectivity of active divider decoupling.

At higher DEM clock frequencies DEM switch settling time starts to get more impact on the averaged bit currents. Attached oscillograms illustrate this. Upper channel shows DEM oscillator output, lower channel shows unfiltered active divider output. Arrows show spike as a result of DEM switch settling time.

So here lower DEM clock frequency is clearly better.

At lower DEM clock frequencies however, RC filter efficiency reduces. The ripple currents that are visible on the lower channels need to be filtered out by the active divider decoupling caps. The higher the DEM clock frequency, the more effective the decoupling cap will be (lower ripple current) up to the point where series inductance will reduce decoupling efficiency.

So lowest DEM clock frequency is set by practical active divider decoupling cap value / size.

In practice we need to make a compromise between DEM clock frequency, impact of DEM switch settling time and ripple current on the active divider decoupling cap.

And with 1uF SMD 1210 size film decoupling caps this happens to be around 60 KHz.
Attached Images
File Type: jpg fdem.jpg (103.1 KB, 892 views)
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Old 11th November 2012, 04:22 PM   #4602
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Hi Sandor

Quote:
They all are 16V, is this safe?
Highest average voltage on active divider outputs (pin 13 and pin 18) equals approx. -7.5V. Voltage on all other active divider outputs is lower. So 16V is safe.

Quote:
Better a PPS (polyphenylene sulphide) or FCA (acrylic) dieletrcic?
I tested both, PPS (Panasonic) and FCA (Cornell Dubilier).

PPS: 16V, -40 to +85 Celcius, Dissipation factor 1.5%, IR > 300M Ohm (Panasonic Datasheet).
http://www.farnell.com/datasheets/31740.pdf

FCA: 16V, -40 to +85 Celcius, Dissipation factor, 1.5%, IR >300M Ohm (Cornell Dubilier datasheet).
http://www.farnell.com/datasheets/199119.pdf

In practice both work equally well.
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Old 11th November 2012, 06:04 PM   #4603
Sandor is offline Sandor  Italy
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Hi John,
thank you for answering.
1) I see that the Cornell-Dubilier datasheet explicitly states that their FCA acrylic film caps are "non-inductive". Could this be a REAL advantage (i.e. not only on paper) over Panasonic capacitors?

2) About the DEM clock frequency: have your ears confirmed the results shown by your scope, at 60 KHz?

3) As far as I understand, each of the decoupling caps should have its own route to pin 5. Is it acceptable to have a small "ground bus" in the center of the TDA1541, routed to pin 5 on one end?

Last edited by Sandor; 11th November 2012 at 06:12 PM.
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Old 12th November 2012, 02:20 PM   #4604
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by Shinja View Post
poobah pointed out the problem of "direct interpolation" at #85 and so on.
Thank you, colleague Shinja
I am a sign with this post. But at these
early reports
was not a refusal of initial concept.

Last edited by SSerg; 12th November 2012 at 02:37 PM.
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Old 12th November 2012, 03:58 PM   #4605
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Hi Sandor,

Quote:
1) I see that the Cornell-Dubilier datasheet explicitly states that their FCA acrylic film caps are "non-inductive". Could this be a REAL advantage (i.e. not only on paper) over Panasonic capacitors?
Both capacitors have stacked film construction (low inductance) and are very well suited for decoupling.

Quote:
2) About the DEM clock frequency: have your ears confirmed the results shown by your scope, at 60 KHz?
Yes, but I have to add that these tests were carried out with a modified free-running DEM oscillator circuit that offers very low jitter compared to the Philips datasheet application (attached oscillograms).

Quote:
3) As far as I understand, each of the decoupling caps should have its own route to pin 5. Is it acceptable to have a small "ground bus" in the center of the TDA1541, routed to pin 5 on one end?
Yes, I also use a GND bus because of limited space for separate GND traces underneath the chip.
Attached Images
File Type: jpg TDA1541A-MK17dem1.jpg (97.9 KB, 820 views)
File Type: jpg TDA1541A-MK17dem2.jpg (98.6 KB, 807 views)
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Old 13th November 2012, 04:00 AM   #4606
tessier is offline tessier  Canada
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Hi -ecdesigns-

I would use the WM8804 with the TDA1541A, but the WM8804 supply voltage are 3.3V.

Your I2S attenuators are designed for 5V TTL levels.

Can you tell me the value of your I2S attenuators resistors for a 3.3V I2S ?

Thanx

Paul
Attached Images
File Type: gif tda1541 dem clock 5.GIF (69.5 KB, 770 views)
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Old 13th November 2012, 05:14 AM   #4607
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Quote:
Originally Posted by -ecdesigns- View Post
Hi studiostevus,

DEM clock frequency does not need to be equal to or a multiple of WS nor BCK. The DEM system can be viewed as a separate module that simply provides binary weighted DC bit currents for each channel.
Although I am by no means an expert, I would think that although the DEM system can be viewed as a separate module (as can be seen indeed in the tda1541a internal schematic), spikes would nevertheless find their way to the substrate.

I realize this reasoning is has been argued by yourself some months ago, and I fully agree with ealier commenter's views on trial-and-error (which led to Edison's bulb), and that it is proper science to test a hypothesis and being honest if the hypothesis proves to be false.

Nevertheless, I would still be interested to understand the current views vs. earlier assumptions related to substrate bounce etc...

Quote:
The reasons I abandoned DEM oscillator synchronization are increased on-chip interference levels
why?
Quote:
and the extra clock load on the super critical clock signals.
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Old 13th November 2012, 11:17 AM   #4608
SSerg is offline SSerg  Russian Federation
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Hi maxlorenz,
Quote:
Originally Posted by maxlorenz View Post
Again, SSerg, I fail to see how your posts contribute to anything at all...in the Universe.
My contribution to development given project is an indication on inexactnesses and errors of the author of the subject.
In than is concluded your contribution? What you suggested? The number of the post?
Quote:
Originally Posted by maxlorenz View Post
This is not a forum for dialectic confrontation but for inventing, sharing and building nice gear to enjoy our beloved music. People who contribute freely to our enjoyment must be thanked and encouraged...
You are not an attorney. The question was addressed an author of the subject. He capable answer the questions itself. And you are not a moderator, not you to solve that possible to write, but that no.
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Old 13th November 2012, 11:19 AM   #4609
SSerg is offline SSerg  Russian Federation
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Hi oshifis,
Quote:
Originally Posted by oshifis View Post
And don't forget the principles described in the initial post
I used the call, which was kept at author message: «please feel free to ask, your comments, tips and reactions are very welcome» (post #1).
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Old 13th November 2012, 12:24 PM   #4610
oshifis is offline oshifis  Hungary
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I call this a negative attitude. A more positive attitude would be something like this:
"Look, I don't like your solution for this and this reason. It can be done better. Here is the circuit diagram, photograph, and some measurements from the prototype of my solution - which I can demonstrate is better than your approach"
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