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Old 16th October 2012, 10:17 AM   #4521
Overeem is offline Overeem  Netherlands
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Hi,

See attached picture of FCTS

Regards,
Marcel
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Old 16th October 2012, 02:00 PM   #4522
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Quote:
Originally Posted by Overeem View Post
Hi,

See attached picture of FCTS

Regards,
Marcel
Hi, Marcel,

The main problem I see with this particular charge-transfer topology is that it still doesn't effectively isolate the powered circuit from A.C. line noise. While C1 is disconnected from the A.C. line by the periodic commutation of D5 and D6, any A.C. line noise still modulates the base of T1. Which means the current supplied to the powered circuit from C1 will be a modulated replica of that noise. The same noise breakthrough mechanism will happen with C2, T2, D7, and D8 during the opposite half-cycle.
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Old 16th October 2012, 03:06 PM   #4523
Overeem is offline Overeem  Netherlands
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Hi Ken,

It's not my design,I just digged this up as was asked for this schema.
It's one of EcDesigns old approaches.

Marcel
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Old 19th October 2012, 10:53 AM   #4524
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by -ecdesigns- View Post
The rise time inside the TDA1541A is determined by its specified limiting frequency of 6.4 MHz. This corresponds with a signal rise time of approx. 56ns.
Hi, -ecdesigns-
How you this has estimated?
According to Philips datasheet (TDA1541A, p.7), rise time (fall time) <32 ns.

Quote:
Originally Posted by -ecdesigns- View Post
Each TDA1541A I2S input has a diode in series that stops conducting when the external signal amplitude exceeds approx. 1.4V. In other words, the external drive circuit is disconnected when the input diode stops conducting.
On the TDA1541A inputs stand the transistors but diodes connected with output of TDA1541A.
See: ″A Monolithic Dual 16-Bit D/A Converter″, ieee journal of solid-state circuits, vol. sc-21, no. 3, june 1986 and see attachment.
Click the image to open in full size.
Quote:
Originally Posted by -ecdesigns- View Post
Based on this, the limiting series resistor value for TDA1541A BCK, WS, and DATA inputs would be 1K8
The value of the resistor must be close to wave resistance of the signal line to prevent the signal reflections. For PCB conductors this resistance has an order 100 ohm (nowhere near not 1k and not 1,8k). 1,8k - in any event too much
It is impossible with impunity enlarge duration a rise time of input signal. This enlarges the uncertainty of the switching, but signifies and jitters.

Serg
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Old 20th October 2012, 07:25 AM   #4525
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Hi SSerg,

Quote:
How you this has estimated?
According to Philips datasheet (TDA1541A, p.7), rise time (fall time) <32 ns.
I used this online calculator:

Pronine Electronics Design - RC Circuit Calculator

Using 6.4 MHz and 12pF (input capacitance). Differences between datasheet and calculation can be explained by the CCS in the I2S input circuit

Quote:
On the TDA1541A inputs stand the transistors but diodes connected with output of TDA1541A.
See: ″A Monolithic Dual 16-Bit D/A Converter″, ieee journal of solid-state circuits, vol. sc-21, no. 3, june 1986 and see attachment.
TDA1541A I2S input circuit is similar to the TDA1543 (attached schematic diagram).

Quote:
The value of the resistor must be close to wave resistance of the signal line to prevent the signal reflections. For PCB conductors this resistance has an order 100 ohm (nowhere near not 1k and not 1,8k). 1,8k - in any event too much
Correct, and in the past I used series resistor values ranging from 22 Ohms to around 150 Ohms. In the Octal DI DAC project I used 22 OHms if I am correct.
The reason I use (much) higher series resistor values is to avoid injecting more RF energy than neccessary for reliable chip operation. I use I2S attenuators with 800mVpp output signal amplitude for similar reason.
TDA1541A still works correctly with series resistors up to 1K Ohm (up to 96 KHz sample rate in NOS). When using 44.1 KHz exclusively TDA1541A still works correctly with series resistors up to 1K8.

I use an extra safety margin by using 560R series resistor for BCK, this will enable sample rates up to 96 KHz NOS (64 bits / frame) or 192 KHz NOS (32 bits / frame).

Quote:
It is impossible with impunity enlarge duration a rise time of input signal. This enlarges the uncertainty of the switching, but signifies and jitters.
Until recently I was convinced that fastest transients would lead to lower trigger uncertainty and thus lower jitter. However, faster transients can result in increased ground-bounce that in turn can lead to even higher trigger uncertainty. So an optimum must be found between transient rise / fall time and generated jitter.

When using fast logic of say 275MHz that drives a slow TDA1541A (6.4 MHz) we run into compatibility issues that can result in high jitter levels. That's why we need I2S signal band limiting and I2S signal attenuation. WS and DATA signals are not used for sample timing and only need to be stable when latched by the BCK signal rising transient, so here fast transients only increase the amount of interference being dumped on the chip substrate as a result of signal transients. This WS and DATA induced ground-bounce can in turn lead to increased on-chip BCK jitter.
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Old 23rd October 2012, 01:53 PM   #4526
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by -ecdesigns- View Post
Using 6.4 MHz and 12pF (input capacitance).


You try to define
rise time under two parameters. This is incorrect. Rise time (slew rate) is defined as minimum three parameters: frequency of the signal, amplitude of the signal and capacity of the load. For sine it is enough three specified parameter.Additional parameters are required for signal with other form, characterizing the signal form. In any event, it is necessary be orientated on producer data.

Quote:
Originally Posted by -ecdesigns- View Post
TDA1541A I2S input circuit is similar to the TDA1543 (attached schematic diagram).
I do not know, as beside TDA1543. But on TDA1541A I have studied much material and can confirm that you mistaken.
Here is circuit (see attachment) from monograph "High-speed and high-resolution analog-to-digital and digital-to-analog converters", R.J van de Plassche, 1989. This work is dedicated to family TDA1540, TDA1541(A). Obviously that diode unites with output, but at the input stands the transistor.

Quote:
Originally Posted by -ecdesigns- View Post
When using 44.1 KHz exclusively TDA1541A still works correctly with series resistors up to 1K8.
As be with reflected signals? Furthermore, signal fronts have too low slew rate. This enlarges jitter.


Quote:
Originally Posted by -ecdesigns- View Post
So an optimum must be found between transient rise / fall time and generated jitter.
Think, you bore in mind that needs the reasonable compromise between rise (fall) time and increased ground-bounce. With this it is difficult not to agree.

Quote:
Originally Posted by -ecdesigns- View Post
WS and DATA signals are not used for sample timing and only need to be stable when latched by the BCK signal rising transient
Do not forget that WS defines the moment of the issue of the output signal. The flutter of this moment of time will bring about front flutter of analog signal. Well it?
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Old 23rd October 2012, 03:12 PM   #4527
koldby is offline koldby  Denmark
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Default Qustion and suggested buffer/levelshift

Hi All

I have been following this thread for some time now. Facinating!
I am currently using a prototype DAC with much of the technique -ecdesign- uses and it is really showing promise (still a prototype with too long wires, bad screening aso.) .

I have a question regarding the DC shift in I/V stage.
Is this capacitor not as much in the signal path as a coupling capacitor?
See the attached schematic.
Depending on the load resistor, it is not even a correct DC coupling , is it?
And if you use a 470 uF coupling cap. and a load of say 100k , isn¨t this as good as a DC coupling (besides the fact that there is a capacitor in the signal path, witch has its problems)

The other thing is a suggestion to a buffer / level shifter to act on the I2S signals.
Again look at the schematic.
The blue led reduces the 5V to 1,8V witch according to John, should be fin for BCK. A green or red could be used on the WS and DATA signals.
The diode below the source resistor raises the signal to about 0,5V. Maybe this is too muc, but a germanium diode could be used.

It is a very clean BCK that comes out of this - look at the pictures. Even from the very rude circuit as seen in the last photo.

Comments?

Koldby
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File Type: jpg 1.jpg (34.8 KB, 216 views)
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Last edited by koldby; 23rd October 2012 at 03:18 PM.
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Old 23rd October 2012, 03:24 PM   #4528
koldby is offline koldby  Denmark
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Forgot to take the bandwith limiter off in the scope.
Here with 60 Mhz bandwith:
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Old 23rd October 2012, 11:25 PM   #4529
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Hello -ecdesigns-

I just found a Pass Lab B1 buffer amp ready made board.

If I do a modification (R4) like in my schematic, can I use it as a IV amp for my TDA1541A ?

Do I need more modifications and which ones ?

Thank you

Bye

Gaetan
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Last edited by gaetan8888; 23rd October 2012 at 11:30 PM.
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Old 24th October 2012, 10:23 AM   #4530
SSerg is offline SSerg  Russian Federation
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Hi to all,
I has decided to look that will if give on DI-DAC square-wave pulse. From diagram is seen that front of the pulse becomes less steep, slew rate falls. The pulse “spreads”.
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Last edited by SSerg; 24th October 2012 at 10:43 AM.
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