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Old 29th September 2012, 07:48 AM   #4501
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Hi studiostevus,

Quote:
- Did you notice any adverse consequences from such overshoot (like for example substrate bounce) ?
Yes.

Clock sources with fast transients need to be adapted for the slower TDA1541A (6.4 MHz limiting frequency) digital inputs. Failing to do so will cause surge currents during signal transients, dumping interference on the chip substrate.

This interference increases on-chip ground-bounce. This in turn increases trigger uncertainty and trigger uncertainly leads to increased on-chip jitter levels. The increased jitter levels are audible (jitter is audible).

The surge currents can also "back-fire" to driver / divider / clock circuits also leading to increased jitter levels in these clock sources.

In other words, the compatibility between clock source and TDA1541A will have direct effect on perceived sound quality as it changes jitter levels in both, clock source and TDA1541A.

In order to reduce ground-bounce caused by external (clock) signals we have to minimise clock frequency (NOS), minimise signal amplitude and make the clock signal compatible with the TDA1541A limiting frequency of 6.4 MHz.

In the latest TDA1541A prototype setup I use RC low pass filters / attenuators on all I2S signals. The C in these filters consists of TDA1541A input capacitance (12pF) plus PCB trace capacitance.

Quote:
Are you using resistors or other means to counter overshoot?
560R ... 1K.
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Old 29th September 2012, 08:00 AM   #4502
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Thanks John for the explanation

560r....1k ?
That must be limiting rise time of the signal quite significantly. Especially on bck this could also cause trigger uncertainty i'd say, no?
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Old 2nd October 2012, 08:23 AM   #4503
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Hi studiostevus,

Quote:
560r....1k ?
That must be limiting rise time of the signal quite significantly. Especially on bck this could also cause trigger uncertainty i'd say, no?
The rise time inside the TDA1541A is determined by its specified limiting frequency of 6.4 MHz. This corresponds with a signal rise time of approx. 56ns.

Each TDA1541A I2S input has a diode in series that stops conducting when the external signal amplitude exceeds approx. 1.4V. In other words, the external drive circuit is disconnected when the input diode stops conducting.

The positive transient is now determined by an internal CCS and input (stray) capacitance. In other words, the CCS needs some time to charge the input capacitance with the given CCS charge current.

This will be the fastest rise time that can be realised on the chip, regardless of the rise time of the external signal.

Connecting a low impedance to the BCK input doesn't help either (input series diode disconnects this impedance from the internal BCK circuit).

Here some examples of limiting frequency and rise time with different series resistor values with 12pF load:

2K2, 6.02 MHz, 60ns
1K8, 7.36 MHz, 49ns <
1K5, 8.84 MHz, 41ns
1K2, 11.052 MHz, 33ns
1K, 13.26 MHz, 27ns
820R, 16.17 MHz, 22ns
680R, 19.50 MHz, 18ns
560R, 23.68MHz, 15ns
470R, 28 MHz, 13ns
390R, 34 MHz, 10ns
330R, 40.19 MHz, 9ns
270R, 28.21 MHz, 7ns
220R, 60.28 MHz, 6ns
100R, 132 MHz, 2.7ns
47R, 282 MHz, 1.3ns

Based on this, the limiting series resistor value for TDA1541A BCK, WS, and DATA inputs would be 1K8

In order to create some margin (PCB trace capacitance) we can settle for approx. 1K. The exact value depends on the stray capacitance on the I2S signal lines and EMI (lower series resistor value increases immunity to EMI).

Another way to further reduce interference being dumped on the chip substrate is reducing I2S signal amplitude. I am now using BCK signal amplitude of 800mVpp with a DC offset of approx. 1V.

I attached an oscillogram of BCK.
Attached Images
File Type: jpg bcknew.jpg (91.4 KB, 896 views)
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Old 9th October 2012, 03:17 AM   #4504
Art is offline Art
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Hi John (ecdesigns),
Regarding your post #4489 about hi-output I/V converter. I'd like to try it, in order to drive a PP EL84.

1. Can I replace BF862 with 2SK117GR? BF862 is not available here.
2. I'll apply to TDA1543. Supply and component value is as follow.

Supply Voltage: 250V
R source = 1.5k and connect to ground.
R drain = 44k
R I/V = 15k
No-signal current of TDA1543 aprox 1.3mA, adjust voltage on 1543's output = 3V, so bias current pass R source = 2mA
Current pass R drain = 5mA, so voltage over R I/V = 1.7mAx15k = 25.5V
Effective R I/V = 44x15/(44+15) = 11.186k
Vpp out = 29.08Vpp

I'll use this output from balance TDA1543, to drive a PP EL84. Your comment and suggestion is very appreciate.
Regards,
Art.
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Old 9th October 2012, 11:32 AM   #4505
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Hi Art,

Quote:
1. Can I replace BF862 with 2SK117GR? BF862 is not available here.
BF862 max. VDS equals 20V so you would have to use a different JFET or MOSFET with suitable VDS.

For JFETS: use adjustable negative gate voltage.
For MOSFETs: use adjustable positive gate voltage.

Suitable MOSFET would be 2SK216 (200V VDS).


Quote:
2. I'll apply to TDA1543. Supply and component value is as follow.
TDA1541A output voltage needs to be 0V, so we can use 0V as reference for the passive I/V resistor without the risk of clipping.

TDA1543 output voltage needs to be half the supply voltage so I/V resistor must be referenced to a 2V5 reference voltage. Then one might as well connect the I/V resistor to +V (say +70V) and use a coupling cap between I/V resistor and phase splitter.

Suggestion for approx. 27Vpp output signal:

70V +V supply (can be derived from tube HV using low noise voltage regulator).
12K passive I/V resistor between +70V and MOSFET drain.
8K2 between -15V and TDA1543 output (2mA extra bias current for MOSFET current buffer).

Coupling cap between MOSFET drain and phase splitter.

Push-Pull stage requires a phase splitter. One can also experiment with 2 x TDA1543 to generate balanced output signals, this way the phase splitter could be removed.
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Old 9th October 2012, 04:03 PM   #4506
Art is offline Art
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Default Hi Output I/V for PP Tube

Hello John,
Thanks for your suggestion. I mean I'll use 2SK117GR.

Yes. I have a balance TDA1543 Non-OS DAC. One TDA1543 for positive R/L signal and another for negative R/L signal. Now, it use op-amp I/V and get balance output to Push-Pull EL84 amplifier. I saw your hi-output I/V idea in post #4489.

I think I can remove op-amp I/V and driver tube for EL84 Amp. Then use your I/V and connect to EL84 directly.

The schematic is attached. Will this idea work? How do you think.
Best Regards,
Art.
Attached Images
File Type: gif Hi_Output_IV.gif (17.5 KB, 732 views)
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Old 9th October 2012, 04:46 PM   #4507
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Quote:
Originally Posted by Art View Post
Hello John,
Thanks for your suggestion. I mean I'll use 2SK117GR.

Yes. I have a balance TDA1543 Non-OS DAC. One TDA1543 for positive R/L signal and another for negative R/L signal. Now, it use op-amp I/V and get balance output to Push-Pull EL84 amplifier. I saw your hi-output I/V idea in post #4489.

I think I can remove op-amp I/V and driver tube for EL84 Amp. Then use your I/V and connect to EL84 directly.

The schematic is attached. Will this idea work? How do you think.
Best Regards,
Art.
Art, the circuit you've designed will have an output impedance of about 11k ohms. That is quite high, and may result in noticeable high frequency roll-off, depending on the amount of lumped shunt capacitance of the interconnect together with that of the input of the next amplification stage.
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Old 10th October 2012, 09:43 AM   #4508
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Hi Art,

2SK117 (not connected to trimmer) gate must be connected to +5V in this setup, or you can leave it out for testing.

2SK117 VDS = 50V, so check if voltage doesn't exceed this limit.

Output impedance would be approx. 11.18K and could be too high as Ken Newton mentioned.

Output impedance can be reduced by increasing full-scale current (paralleling DAC chips) and lowering I/V resistor value.

You can also try placing a suitable unity gain buffer with low input capacitance and high input impedance between I/V resistor and EL84.

It would be better to create 2mA bias current by using say -15V supply and 9K series resistor. This way the impedance of the passive bias current source can be increased.
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Old 10th October 2012, 02:49 PM   #4509
Art is offline Art
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Hi Ken, John
Thank you very much for your suggestion.

Ken, output (after coupling cap) will be connected to EL84 by a 3-4 cm wire and EL84 have input capacitance just 10-12pF. Do you think the HF will be roll-off?

John, what's the benefit if the impedance of the passive bias current source increase? and Please suggest how to build -unity gain buffer with low input capacitance and high input impedance-. I' just know that tube and JFET have low input C and high input impedance, compare to Tr and MOSFET, but no idea how to.

Best Regards,
Art.
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Old 11th October 2012, 06:40 PM   #4510
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Quote:
Originally Posted by Art View Post
Ken, output (after coupling cap) will be connected to EL84 by a 3-4 cm wire and EL84 have input capacitance just 10-12pF. Do you think the HF will be roll-off?

Best Regards,
Art.
With such low shunt capacitance, the the -3dB frequency of this coupling will be in the vicinity of 800kHz, so you will not have any problem with audible HF roll-off.
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