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Old 7th September 2012, 02:02 PM   #4491
jstang is offline jstang  United States
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Am I going to have to drop my 6dj8 output in favor of John's latest FET circuit....

Jk
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Old 9th September 2012, 09:58 AM   #4492
JOSI1 is offline JOSI1  Germany
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Quote:
Originally Posted by -ecdesigns- View Post
Hi ryanj,

I attached MK14 I/V circuit schematics.
T10 and T11 form a cascode current buffer. P1 sets DC voltage at DAC output at 0V DC. Bandwidth approximates JFET Ft (715 MHz).
Hi John,
is it correct that R3=15K is connected to a positive voltage (+5V) to adjust the DAC output voltage to 0V.
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Old 9th September 2012, 07:08 PM   #4493
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Hi JOSI1,

Quote:
Hi John,
is it correct that R3=15K is connected to a positive voltage (+5V) to adjust the DAC output voltage to 0V.
Yes this is correct, T11 gate voltage can be varied between 0V and +312mV
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Old 10th September 2012, 09:47 AM   #4494
galeb is offline galeb  Spain
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Could you post the complete schematic of the DAC part?

Kind regards,
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Old 11th September 2012, 10:10 AM   #4495
ryanj is offline ryanj  Australia
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Quote:
Originally Posted by -ecdesigns- View Post
Hi ryanj,

The input impedance of a grounded-gate circuit equals approx. 1 / gm. So current buffer input impedance equals approx. 1 / 0.045 = 22 Ohms. With 4mA full-scale current, max. ac voltage amplitude on TDA1541A current output equals 0.004 * 22 = 88mV or +/- 44mV.

1.94Vpp with 500R passive I/V resistor and PCS impedance of 16,400 Ohms.
Thanks for the detailed reply and posting your IV schematics.

Sorry, what i meant when i asked what the voltage is on the output of the DAC, i meant; What is the measured DC Voltage on pin 6 , and 25 of the TDA1541A, and how stable is this DC offset? Are you getting better than +-5mV in various temperatures?

Also, are you finding that what impedance the TDA1541A sees on its output (pin 6, 25) is clearly better (in terms of measured performance and listening test) when lower?

At one point you were finding that having -40 ...-48mV DC on the AOL, AOR pins measured better on your distortion meter, what are your latest findings with your current setup? Do you have any other measurements you could share?

Thanks again for sharing your work John.

Regards, Ryan
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Old 15th September 2012, 07:55 AM   #4496
Zoran is offline Zoran  Serbia
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excellent visual appearance EC
clear and compact
I like it on the first site
thanks
(amazing job you are doing, showing a enormous will, determination, knowledge, skill
in different areas....)
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Old 15th September 2012, 07:10 PM   #4497
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John, I am using a Johnson counter on the bck line. I have noticed I have some overshoot on the square wave. I am not using any resistors between the (SN74AUC1G74) flipflops, nor in the line to the TDA.

- Did you notice any adverse consequences from such overshoot (like for example substrate bounce) ?

- Are you using resistors or other means to counter overshoot?

Thanks!
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Last edited by studiostevus; 15th September 2012 at 07:15 PM.
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Old 17th September 2012, 11:12 PM   #4498
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Sounds like the power supply has series R's on both the hot and ground leg of the RC filtering stage, for the + and - supplies. I like to put the RC stage before the first active device to keep RFI out of the PN junction.
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Old 22nd September 2012, 03:54 PM   #4499
JOSI1 is offline JOSI1  Germany
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Default SD8 Power Supply

Hello John,

Quote:
Originally Posted by -ecdesigns- View Post
Latest developments,

The power supply module provides a number of isolated, very clean currents for the local discrete shunt regulators. Each supply now consists of a transformer with pre-post filtering, 4th order capacitance multiplier followed by 3rd or 4th order balanced RC filters / current limiters.
Does the 4th order capacitance multiplier consist of 4 single cap multilpiers (R/C/Darlington) placed alternately in the negative line and the positive line?

Quote:
The positive bias current is obtained by a 115V DC supply with 16K4 series resistor.
Can You post a schematic of the 115V DC supply or explain in more detail how the 115V DC supply looks like.
I guess you are using a circuit to double the voltage (e.g. Delon).
How do You filter/stabilize the 115V DC supply?

Many thanks for your support.
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Old 24th September 2012, 07:37 AM   #4500
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Hi ryanj,

Quote:
Sorry, what i meant when i asked what the voltage is on the output of the DAC, i meant; What is the measured DC Voltage on pin 6 , and 25 of the TDA1541A, and how stable is this DC offset? Are you getting better than +-5mV in various temperatures?
The DC voltage on the DAC output can be adjusted so the ac signal swings symetrically around 0V DC. Depending on the circuit this requires a specific DC offset. The stability of the resulting DC voltage on the TDA1541A mainly depends on accuracy of the power supplies (-15V, +5V, and +115V).

Quote:
Also, are you finding that what impedance the TDA1541A sees on its output (pin 6, 25) is clearly better (in terms of measured performance and listening test) when lower?
With passive I/V resistor connected between TDA1541A output and ground, the output signal is in parallel with the DAC output. So when the DAC output clips (diode transistor bit switch properties) the output signal clips. By using an external +2mA bias current the tolerable ac signal amplitude on the TDA1541A can be doubled.

When clipping occurs it results in non-linear distortion of the ac signal on the TDA1541A output. This leads to inter-modulation distortion.

With a cascode current buffer, the I/V resistor connects to the cascode current buffer output. Here, large ac signal swings are no problem. The cascode current buffer "isolates" The I/V resistor from the TDA1541A output by presenting a low impedance to the TDA1541A output and a high impedance to the passive I/V resistor.

Quote:
At one point you were finding that having -40 ...-48mV DC on the AOL, AOR pins measured better on your distortion meter, what are your latest findings with your current setup? Do you have any other measurements you could share?
Since there will always be an ac voltage present at the TDA1541A output, It is best to tune DC offset for symmetrical ac voltage swing (output compliance -25mV and +25mV or 50mVpp). The DC offset on the TDA1541A output depends on the application.
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