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Old 1st September 2012, 10:16 PM   #4481
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Thank you, s3tup. I will try it.

Sincerelly yours,
M.
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Old 3rd September 2012, 02:52 PM   #4482
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by -ecdesigns- View Post
I didn't mention that we get more information out than we put in. I just mentioned that the output sample rate can be increased to 88.2, 176.4, or 352.8 KHz and that the output bit resolution can be theoretically increased to 17, 18, or 19 bits.
Hi, -ecdesigns-

I seem that at given fragment you, colleague, to itself disagree.
Possible, here case in unchancy terminology.

Yes, signal becomes more smooth, but this does not mean increase the resolution of the system.

Given system not to call back on change the input signal at a level of seventeenth bit.

The maximum what possible obtain from 1541 - get the real resolution of the output signal 16 bits.
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Old 3rd September 2012, 03:29 PM   #4483
jstang is offline jstang  United States
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I have a CD-PRO and use i2s. It's a 48 bit word, so unfortinutely the 4517 would not work for me...I used discrete one bit shift registers. But it does clock slower...

jk

Quote:
Originally Posted by maxlorenz View Post
The DI4JM (scrambler/interpolator DAC) is not bad either. It also can be converted easily to DI2*4JM...

[IMG]http://https://picasaweb.google.com/...eat=directlink [/IMG]

[IMG]http://https://picasaweb.google.com/...eat=directlink [/IMG]

Cheers,
M.
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Old 3rd September 2012, 04:00 PM   #4484
SSerg is offline SSerg  Russian Federation
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Quote:
Originally Posted by s3tup View Post
Right click on image - copy image url (in chrome). You need to get a link which ends with .gif or .jpg.

Hi, s3tup
I see, you time in vain did not lose.

Serg
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Old 3rd September 2012, 05:11 PM   #4485
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Uh oh, my time management s*cks

As for real resolution of >16 bits - it could be obtained thru oversampling, with a proper digital filter which would support 16>bit input, 16bit output with time interleaving "noise shaping" of the extra bits. Multibit deltasigmas work this way, kinda. For doing this, we'll need some DSP (FPGA), with an output for each DAC IC.
The straight multiple-DACs with delayed output thing will create a short FIR-like low-pass filter - 4 DACs = 4 taps, that's what we see on the scope shots. If we'll play with the I/V conversion ratios for each DAC, we could shape the filter's response, but again - it's just 4 taps
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Old 6th September 2012, 08:10 AM   #4486
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Latest developments,

I added some pictures of SD8-project progress.

The power supply module is finally completed and I am now making the housing. The housing consists of CNC milled 3mm thick aluminium sheets and CNC milled wooden parts that are fixated on hexagonal spacers. The front panel housing consists of eight pieces of wood, the base of 9 pieces of wood. After fixating the wooden segments are sanded for over an hour to get a smooth finish.

I still have to make the front panel keys, top plate and insulator plate for the RCA sockets.

I added ventilation slots in the housing that provide convection cooling. The TDA1541A chip is cooled through the aluminium front panel and can remain powered-on.

The SD8-player has latest TDA1541A-MK14 DAC installed. This DAC has 44.1 KHz synchronised DEM clock and a new I/V converter.

The I/V converter is built around a RF JFET cascode current buffer that places a low impedance on the TDA1541A output. Two passive current sources are added to provide 2.6mA negative bias current and 7mA positive bias current.

I tested many conventional CCS circuits and none of these were able to offer natural and transparent sound quality. The best sounding conventional CCS circuits were the simplest one's (one JFET or one transistor with LED reference). The more complex the CCS circuit, the worse the resulting perceived sound quality. The problem could be non-linear impedance and / or feedback loop delays. Passive CCS has no feedback loops, only a power supply and a single resistor.

The positive bias current is obtained by a 115V DC supply with 16K4 series resistor. The 500R passive I/V resistor is connected to cascode current buffer output / positive bias current and GND. Output voltage is now 2Vpp but can be increased by increasing passive I/V resistor value. 2K2 I/V resistor would give 8.8Vpp for example.

The power supply module provides a number of isolated, very clean currents for the local discrete shunt regulators. Each supply now consists of a transformer with pre-post filtering, 4th order capacitance multiplier followed by 3rd or 4th order balanced RC filters / current limiters. There is a separate switchable 5V supply for remote ON / OFF (mono blocks).
Attached Images
File Type: jpg sd8-9.jpg (106.8 KB, 965 views)
File Type: jpg sd8-10.JPG (100.9 KB, 928 views)
File Type: jpg sd8-11.jpg (100.5 KB, 831 views)
File Type: jpg sd8-12.jpg (93.6 KB, 820 views)
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Old 6th September 2012, 12:06 PM   #4487
ryanj is offline ryanj  Australia
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Hi John, nice work.

I'm pretty curious to understand more about your new CCS, and your IV stage. Whats it input impedance of the IV stage? What voltage have you now got on the analog output of the DAC? How thermally stable is the CCS? Whats the benefit of having the CCS running off 115VDC?

I would love to see some schematics if i may.

Ryan
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Old 6th September 2012, 05:05 PM   #4488
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Hi John,
Thank you. Good news. Will you post schematics of the latest developments?
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Old 7th September 2012, 11:37 AM   #4489
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Hi ryanj,

Quote:
Whats it input impedance of the IV stage?
BF862 has yfs of 45 (typical) and Ft of 715 MHz. So we have both, high gain and high limiting frequency. That's why I chose this specific JFET for this application.

The input impedance of a grounded-gate circuit equals approx. 1 / gm. So current buffer input impedance equals approx. 1 / 0.045 = 22 Ohms. With 4mA full-scale current, max. ac voltage amplitude on TDA1541A current output equals 0.004 * 22 = 88mV or +/- 44mV.

Quote:
What voltage have you now got on the analog output of the DAC?
1.94Vpp with 500R passive I/V resistor and PCS impedance of 16,400 Ohms.

Quote:
How thermally stable is the CCS?
It is actually a Passive Current Source based on a stabilised voltage and a series resistor. Thermal drift is very low (combination of both, power supply and resistor thermal drift). Thermal drift is much lower compared to a CCS.

Quote:
Whats the benefit of having the CCS running off 115VDC?
The higher the series resistor value (impedance) the more the PCS resembles an ideal CCS.

The problem is that when using relatively low voltage and relatively high series resistor value, the target current may not be obtained (too low). By increasing the supply voltage target current can be obtained and impedance can be increased.

Example:

3mA target current, 20V supply and 1V DC across the load would require 19 / 0.003 = 6K333 resistor. So the PCS impedance would now be 6K333.

3mA target current, 200V supply and 1V DC across the load would require 199 / 0.003 = 66K333. Now the PCS impedance is raised to 66K333 while maintaining target output current of 3mA.

Advantages of a PCS:

- Constant impedance over very large frequency range (use of RF resistors extends range).
- Instant response, no feedback loops, no delays.
- Very low distortion.
- Very low thermal drift.
- Very low noise.

Quote:
I would love to see some schematics if i may.
I attached MK14 I/V circuit schematics.

T10 and T11 form a cascode current buffer. P1 sets DC voltage at DAC output at 0V DC. Bandwidth approximates JFET Ft (715 MHz).

R4 sets negative bias current of -15 / 5600 = -2.7mA. PCS impedance equals 5600 Ohms and is in parallel with 22 Ohm cascode current buffer input impedance.
R1 and R2 set positive supply current of +7mA, PCS impedance equals 16,400 Ohms and is in parallel with 500 Ohm passive I/V resistor so actual I/V resistor value is reduced to 485 Ohms.

The cascode current buffer output current is fed to the 500 Ohm passive I/V resistor that connects to GND.

Current / voltage swing:

DAC output current = 0mA (minimum current), I/V resistor current equals +7mA - 2.7mA = +4.3mA, voltage across I/V resistor equals +2.0855V
DAC output current = 2mA (bias current - no signal), I/V resistor current equals +7mA - 2mA - 2.7mA = +2.3mA, voltage across I/V resistor equals +1.1155V
DAC output current = 4mA (full-scale), I/V resistor current equals +7mA - 4mA - 2.7mA = +0.3mA, voltage across I/V resistor equals +0.1455V


The +115V supply now enables higher output amplitude.

Example:

10K passive I/V resistor. DC voltage (2mA bias) equals 20V. PCS series resistor equals (115-20) / 0.007 =13K57. This resistor is in parallel with 10K so I/V resistor value drops to 5.76K
Output amplitude now equals 0.004 * 5760 = 23.4Vpp.

This opens the possibility of using a unity gain bridge buffer (Circlotron) instead of a conventional amplifier to drive the speakers. With 23Vpp on each bridge half we would get approx. 16V rms. This would give approx. 32 watts rms in 8 Ohms.

When using 2 x TDA1541A (phase / anti-phase outputs) it would only take two power MOSFETs and a power supply to drive the speaker.
Attached Images
File Type: jpg ivnew.jpg (49.2 KB, 815 views)

Last edited by ecdesigns; 7th September 2012 at 11:46 AM.
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Old 7th September 2012, 12:07 PM   #4490
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Quote:
This opens the possibility of using a unity gain bridge buffer (Circlotron) instead of a conventional amplifier to drive the speakers. With 23Vpp on each bridge half we would get approx. 16V rms. This would give approx. 32 watts rms in 8 Ohms.

When using 2 x TDA1541A (phase / anti-phase outputs) it would only take two power MOSFETs and a power supply to drive the speaker.
Yeah, baby! Groovy!

[image]http://www.austinpowers.org/wordpres...ers_Series.jpg[/image]

[image]http://www.austinpowers.org/wordpres...n-powers-7.jpg[/image]

Brilliant solutions, Boss.

Cheers,
M.
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