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Old 2nd July 2012, 06:53 AM   #4421
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Hi studiostevus,

Quote:
Well have a look here....

Upper trace: pin16 (dem)
Lower trace: pin bck

Doesnt look good.... Does it?
The signal on the DEM oscillator shows that the DEM oscillator isn't functioning like it should. One should measure a clean sawtooth-shaped signal.

I attached an oscillogram of the DEM clock synced with 2.8224 MHz measured on the MK11 DAC.

Next oscillogram shows DEM clock synced with 352.8 KHz from an earlier design. The spikes on the active divider output signal (filter cap removed) are caused by on-chip crosstalk with BCK.

Easy way to check if the oscillator is actually providing clock pulses to the shift registers and bit switches is removing one of the (100nF) filter caps and checking for step-shaped signal using sensitivity of 20mV / div.

Synchronizing a DEM oscillator with external clock signals isn't easy. The synchronizing circuit must be carefully matched with DEM oscillator properties.
Attached Images
File Type: jpg newdem.jpg (73.1 KB, 793 views)
File Type: jpg dem352.jpg (37.1 KB, 684 views)
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Old 2nd July 2012, 07:55 AM   #4422
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Default power supply question

John

how do you compare your last discrete shunt regulator posted Building the ultimate NOS DAC using TDA1541A with led referenced regulator posted Building the ultimate NOS DAC using TDA1541A either measure bandwidth and impedance and perceived sound
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Old 2nd July 2012, 08:52 AM   #4423
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Hi samoloko,

Quote:
how do you compare your last discrete shunt regulator posted Building the ultimate NOS DAC using TDA1541A with led referenced regulator posted Building the ultimate NOS DAC using TDA1541A either measure bandwidth and impedance and perceived sound
Shunt regulator has advantage that C-E or S-D stray capacitance is in parallel with the connected load and thus helps to decouple the output voltage.

In series regulators the C-E or S-D stray capacitance helps to feed unwanted noise into the connected load.

CCS also puts C-E or S-D stray capacitance between noisy transformer secondary and shunt regulator. That's why I now use capacitance multiplier circuits for ripple rejection (these still pass RF noise through C-E stray capacitance) followed by a balanced RC filter that offers low pass filtering and current limiting for the shunt regulator.
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Old 2nd July 2012, 07:58 PM   #4424
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Quote:
Originally Posted by -ecdesigns- View Post
Hi JOSI1,



Like I mentioned in previous post, DEM clock can be synchronized with either BCK or WS.

In previous designs I triggered or synchronized the DEM clock with BCK.

This has some disadvantages as s3tup pointed out in post #4405.

Electronic switches in active divider cause switching spikes on the averaged output signal. These spikes have specific pulse width. The higher the DEM clock rate the more these switching spikes will dominate the active divider output signal shape.

Cleanest sample steady current could be obtained by synchronizing the DEM clock with WS, then we would add only 2 fixed switching spikes to the already present 128 spikes from BCK (130 switching spikes in total). This means that one DEM cycle (4 switch changes) is completed after every 4 samples.

Other advantage is that the filter caps and filter circuit become less critical as DEM clock rate is now reduced to 44.1 KHz (NOS).

Based on filter cap value of 100nF @ 200,000 Hz, DEM clock rate of 44,100 Hz would require 470nF filter caps (closest value). Since I already had 1uF filter caps installed I could easily test 44.1 KHz DEM clock with minimum changes to the existing circuit.


The DEM circuit ensures that the 6 MSBs plus the input current for the 10 bit passive current divider always remain very closely matched, despite on-chip tolerances / chip aging. Keep in mind that even slightest errors in MSBs also lead to errors in the LSB range. So all bits contribute to the final bit accuracy.



The DEM oscillator now oscillates on the timing capacitor again, so 2K2 resistors need to be removed. For synchronization with WS, 33pF timing cap value is no longer valid.
In short, i conclude the following:

1. Fdem should be as low as possible, but at least f_ws.

2. Although you call it synchronized, it essentially is a free running oscillator with frequency close to ws.

3. Cosc should be quite high to achieve such frequency (470nf Cosc gives 176khz, no?)

3. The filter caps should at least be 470nf in order to provide adequate filtering to allow such low dem frequency.

Just trying to distill the learnings for myself here....
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Old 7th July 2012, 04:11 PM   #4425
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I just tried free running DEM oscillator using a 10nf cap, which results in approx 120khz.

Some observations:
- digital artifacts on low level signals have disappeared, sound is good again
- measuring at pin 16 gives the normal oscillator picture, so it is working
- i had a good look with the scope on pin 16 whether there were any peaks visible on the dem osc signal on the transients of bck... There were not, there is no visible crosstalk, even using this non-synchronized frequency (120khz)
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Old 7th July 2012, 05:04 PM   #4426
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Quote:
Originally Posted by studiostevus View Post
In short, i conclude the following:

1. Fdem should be as low as possible, but at least f_ws.

2. Although you call it synchronized, it essentially is a free running oscillator with frequency close to ws.

3. Cosc should be quite high to achieve such frequency (470nf Cosc gives 176khz, no?)

3. The filter caps should at least be 470nf in order to provide adequate filtering to allow such low dem frequency.

Just trying to distill the learnings for myself here....
really 470 nF (thousand times as much as the spec sheet)?
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Old 7th July 2012, 05:41 PM   #4427
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Quote:
Originally Posted by triode_al View Post
really 470 nF (thousand times as much as the spec sheet)?
pF
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Old 7th July 2012, 05:57 PM   #4428
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So, the issue was in running the DEM with too high rate?
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Old 7th July 2012, 06:01 PM   #4429
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Quote:
Originally Posted by s3tup View Post
So, the issue was in running the DEM with too high rate?
Seems like it yes. I am using a 1998 chip, but 33pf (3mhz?) seems to be too much, even in what i believe to be a good layout.

I am wondering though where to take the dem frequency, considering that i didnt find any evidence of crosstalk (which was the prime reason of choosing a dem frequency equal to either bck or ws or a multiple of these)... Does it not matter what frequency is chosen after all?
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Old 8th July 2012, 06:51 AM   #4430
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Hi studiostevus,


Quote:
1. Fdem should be as low as possible, but at least f_ws.
DEM oscillator produces pulses (rising and falling edge of clock signal) that crosstalk to other on-chip circuits and also appear on the DAC output. These are the 40mVpp spikes that are visible on oscillogram in post #4421 showing the step signal measured on one of the 14 -unfiltered- active divider outputs.

The higher the DEM oscillator rate with respect to WS, the more "spikes" appear on other on-chip circuits, the more interference through crosstalk is generated.

With higher DEM oscillator rates, the impact of given switching pulse width and finite switching time will distort the signal shape at the active divider outputs. The switching spikes are relatively large compared to total switch closed time and the current needs some time to settle after switching, so the flat current steps now turn into a curved signal as the bit current has too little time to settle between switch changes.

When DEM oscillator frequency drops below 20 KHz there is the risk of audible crosstalk in the audio band as DEM oscillator now runs on a frequency that falls within the audio band.

Free running DEM clock can result in DEM oscillator transients coinciding with the latch trigger signal. This in turn can change the exact moment of latching (crosstalk) and thus increase unwanted on-chip jitter.

The TDA1541A output latch is triggered (exact moment the output sample value changes) on the first positive going edge of BCK -after- WS has gone from "1" to "0".

Quote:
2. Although you call it synchronized, it essentially is a free running oscillator with frequency close to ws.
After it's synchronized with WS or BCK, the DEM oscillator is locked to these signals and is therefore no longer free running.

Quote:
3. Cosc should be quite high to achieve such frequency (470nf Cosc gives 176khz, no?)
470pF gives around 200 KHz. I used 33pF for 2.8224 MHz.

Quote:
I just tried free running DEM oscillator using a 10nf cap, which results in approx 120khz.
10nF (0.01uF, 10,000pF) gives around 8 9 KHz. This requires filter cap value of around 2.2uF for each of the 14 active divider outputs.

Quote:
- i had a good look with the scope on pin 16 whether there were any peaks visible on the dem osc signal on the transients of bck... There were not, there is no visible crosstalk, even using this non-synchronized frequency (120khz)
The crosstalk (peaks) I mentioned were measured on the one of the 14 active divider outputs with -filter cap removed-. The amplitude is around 40mVpp. Peaks cannot be measured on pin 16 / 17 as the peaks are caused by the DEM oscillator itself.

Quote:
Seems like it yes. I am using a 1998 chip, but 33pf (3mhz?) seems to be too much, even in what i believe to be a good layout.
All TDA1541A chips have to meet similar specs (max. frequency) so all TDA1541A chip DEM oscillators should run perfectly on 2.8224 Mhz as this is well within max. frequency of around 7 MHz.
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