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Old 25th June 2012, 09:44 AM   #4401
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Well... I had DEM running at 2.8Mhz before, using a former scheme published by John, and I never noticed any distortion/noise on low level signals. Did anyone of you built this latest version, or are John and I the only ones who tested this?
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Old 25th June 2012, 06:04 PM   #4402
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Hi s3tup,

Quote:
what they mean by "DEM reclocking" is not the reclocking itself, but forcing TDA's "dynamic element matching" circuitry to run with external clock. So the DEM averaging will always contain at least 4 steps for each sample (herein it's rate should be 4Fs or greater, there are just 4 positions of current dividers).
The description DEM reclocking is indeed incorrect, DEM oscillator synchronization would be a better description.

The DEM (Dynamic Element Matching) circuit dynamically matches the passive divider output currents for the 6 MSBs only. Philips developed this technique in order to offer high accuracy without the need for expensive (LASER) trimming.

The remaining 10 LSBs are -not- corrected by DEM and are derived from passive dividers. Passive dividers are used to derive binary weighted bit currents (2mA, 1mA, 0.5mA, 0.25mA and so on) from a single current reference source. These binary weighted bit currents are later combined by bit switches to obtain 65,536 possible current levels between 0 and -4mA. With no signal applied, the DAC bias current equals -2mA.

The DEM clock drives shift registers that in turn control an active divider switch matrix. The outputs of these active dividers are averaged / filtered by a RC filter. The active divider outputs provide a constant filtered DC current so there is basically no direct need to complete a full switch matrix cycle for each sample duration.

All an active divider does is averaging between 4 unmatched input currents from a passive divider, providing 4 closely matched output currents at the switch matrix outputs.

So it basically does this:

I out 1 = (I in1 / 4) + (I in 2 /4) + (I in3 / 4) + (I in4 /4)
I out 2 = (I in2 / 4) + (I in 3 /4) + (I in4 / 4) + (I in1 /4)
I out 3 = (I in3 / 4) + (I in 4 /4) + (I in1 / 4) + (I in2 /4)
I out 4 = (I in4 / 4) + (I in 1 /4) + (I in2 / 4) + (I in3 /4)

Addition is done by changing switch positions in the switch matrix, division is done by so called time division (each switch is closed for a specified amount of time).

This also means that slightest deviations in DEM clock rate (jitter) will lead to slight time division errors and thus reduced matching. This is corrected to certain extent by the RC filter.

Unfortunately a 1st order RC filter like used on the active divider outputs offers insufficient attenuation of ripple current (must remain well below 40nA in order not to mask LSB).

Since the filter only offers 6dB attenuation, ripple current always seeps through and leads to an unwanted ripple current on the MSBs. So DEM circuit accuracy depends heavily on how effectively this ripple current can be attenuated. Note that 1 LSB represents only 40nA.

Other problem is that all capacitors distort (they are imperfect). Some major causes are mechanical resonances in charged foils, piezoelectric effects, and low level signal processing limitations.

Ripple current is proportional to passive divider mismatch, so more accurate DAC chips like the TDA1541A-S2 or DAC chips from more recent production series should provide lower ripple current under similar conditions.

Ground noise is also directly coupled into the active divider outputs through the filter cap (low impedance). So in practice it will be extremely difficult to get ripple current levels at the active divider output down to acceptable levels. This is why TDA1541A applications are extremely critical and many conventional TDA1541A applications will certainly suffer from reduced low level performance. This is not caused by the DAC chip but is simply a result of poor design.

Higher value filter caps could be a possible solution provided their reactance is low enough and traces are kept short enough to maintain required low impedance at RF (200 KHz and up). Most physically large decoupling caps with long traces fail to offer low enough impedance for effective decoupling at RF.

Quote:
The DEM isn't supposed to run this way, and it's native frequency is around 300-700kHz, self oscillating and running free.
Apart from the active divider output ripple, there will also be inter-modulation / crosstalk between DEM oscillator and the DAC output signal and DEM oscillator and I2S timing signals.

Listening tests clearly showed that higher DEM clock rates lead to cleaner more refined sound reproduction.

TDA1541A limit frequency (for all circuits) is around 7 MHz this includes the DEM oscillator.

Since I wanted to avoid inter-modulation between BCK and DEM oscillator I changed the value of the DEM oscillator timing cap to approx. 33pF and then synchronized the DEM oscillator with 2.8224 MHz BCK signal.

Forcing the DEM oscillator (triggering) failed as it caused spurious oscillations and interference being dumped on the chip substrate.

DEM oscillator synchronization is extremely critical and since there is no provision for an external DEM clock signal we have to use the timing cap inputs one way or the other.

Quote:
What studiostevus did is connected the BCLK directly to DEM, and forced it to run on 2.8MHz which is a bit more than 300-700kHz, hence his strong suspectism.
Simply connecting BCK to pins 16 or 17 using a coupling capacitor will not work for sure, it will disrupt DEM oscillator circuit operation and degrade BCK signal (increased BCK jitter). Distortion would be accordingly.
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Old 25th June 2012, 07:44 PM   #4403
nowhere is offline nowhere  Israel
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Quote:
Originally Posted by s3tup View Post
nowhere,
what they mean by "DEM reclocking" is not the reclocking itself, but forcing TDA's "dynamic element matching" circuitry to run with external clock. So the DEM averaging will always contain at least 4 steps for each sample (herein it's rate should be 4Fs or greater, there are just 4 positions of current dividers).

The DEM isn't supposed to run this way, and it's native frequency is around 300-700kHz, self oscillating and running free.
What studiostevus did is connected the BCLK directly to DEM, and forced it to run on 2.8MHz which is a bit more than 300-700kHz, hence his strong suspectism.
Does your explanation disprove my statement that clock problems affect more or less the same both weak and strong signals ?
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Old 25th June 2012, 09:55 PM   #4404
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Quote:
Originally Posted by -ecdesigns- View Post
Simply connecting BCK to pins 16 or 17 using a coupling capacitor will not work for sure, it will disrupt DEM oscillator circuit operation and degrade BCK signal (increased BCK jitter). Distortion would be accordingly.
I realize that... my setup is as follows:

BCK to pin 16 via a 12k resistor in series, with a 2k2 resistor to -15V in parallel.

pin16 and pin17 connected to each other using 33pf cap.
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Old 25th June 2012, 10:34 PM   #4405
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nowhere, you are right, jitter affects all signal levels.
I've tried to clear-out that the "reclocking" word in "DEM reclocking" statement is more about syncing the DEM to Fs*X rate rather than fighting the jitter.

-ecdesigns-,
It's kinda weird you've got better results with higher DEM rate...

By increasing the DEM rate 4 times, you increase the amount of emissions by the same 4 times (slew rates stay the same, rate of changes increase 4x, so amount increases 4x).
4x higher frequency = 4x better coupling into surrounding circuits (stray capacitance stays the same, higher frequency = better coupling).
By increasing DEM rate, you go higher into RF zone with more uncontrollable parasitics around.

Maybe it's due to undersized DEM-decoupling capacitors...
When you rise the DEM frequency 4x times, you go to lower impedance zone for DEM caps = 1/4 of original impedance, hence the better decoupling.
r(impedance)=1/2*Pi*f*c for low-frequency part of "V"-shaped capacitor impedance graph.
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Old 26th June 2012, 10:01 AM   #4406
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DEM synchronisation to fs has very big problem, error after DEM work has no averaging! (as it has when DEM clock is asynchronous to fs).
And if you "cook" you 1541 maximally good, the resulting sound quality with DEM sync is definitely worse then with asynchronous (free running) DEM clock.
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Old 26th June 2012, 10:50 AM   #4407
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Nazar_lv, even if we cycle thru all 4 positions during the LRCLK?
It should perfectly average for single sample...

But it won't average for a couple of samples. The error in DEM will be sample-correlated and will be constant for every same sample.
DEM should run freely if we want to get averaging between samples too...
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Old 26th June 2012, 12:19 PM   #4408
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Not strictly related to DEM, I want to point to the important role of MSB. It is also called "sign bit", and it keeps changing on/off when the analog signal is at the lowest level. In contrast, the next significant bit changes at +/- 1/2 full scale, so it has no influence on low level analog signals. My conclusion is that the circuit associated to MSB should be treated with much higher percision that the other passive dividers.
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Old 26th June 2012, 04:24 PM   #4409
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Hi Nazar_Iv,

Quote:
DEM synchronisation to fs has very big problem, error after DEM work has no averaging!
There is no need to complete a DEM cycle "within" a sample period. CD players with this chip and 4 * fs run on 176.4 Khz sample rate.

DEM clock equals approx. 200 KHz and a complete DEM cycle takes 4 clock pulses to complete (approx. 50 KHz rate)

So it typically takes approx. 3.5 samples to complete a DEM clock cycle.

It is possible to use 2KHz DEM clock rate with 10uF decoupling caps or 200 Hz DEM clock rate with 100uF decoupling caps or 44.1 KHz DEM clock rate with 470nF decoupling caps.

The trick is the decoupling cap that smoothens the output signal similar to a smoothing cap placed after a rectifier.

This results in an average bit current (DC) with very small ripple current (AC) super imposed on it.

However, these small ripple currents end up on the DAC outputs and mess-up the output signal (inter-modulation).


Quote:
And if you "cook" you 1541 maximally good, the resulting sound quality with DEM sync is definitely worse then with asynchronous (free running) DEM clock.
TDA1541A is based on current mode logic (CML). Property of current mode logic is that power consumption remains fairly constant (but higher compared to CMOS) regardless of clock frequency. So nothing gets "cooked". I also stay well within TDA1541A limit frequency of approx. 7 MHz so reliable switching is guaranteed.

it is not so easy to correctly synchronize the DEM oscillator with an external clock. So it is likely that a synchronized DEM clock circuit simply doesn't work as it should. Then "synchronized" DEM clock circuits often perform worse compared to the Philips data sheet application.

This however doesn't mean that all DEM clock synchronization circuits perform bad by definition.
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Old 26th June 2012, 05:03 PM   #4410
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The "cook" he referred to was for "good implementation" rather than "die in flames"
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