Building the ultimate NOS DAC using TDA1541A

I am about to build the last I2S to simultaneous version of John
Good I tried TS mode opperation with '40 and '41A too, and it was clearly better than in I2S mode (for '41A).
Probably because latching is same for both ch, and stopped clock...
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(If the frame is 64bit and word for conversion is 16 bits, in the I2S where BCK is constantly present, than we have (64-16)x2=96 more spikes and ground bounces in just one Fs cycle.)
 
!?!? I read about this before. Are you sure?

Instead of averaging the error of the MSB's across time so that one sample ideally has four DEM periods (too fast is a problem), or totally randomising it (free running oscillator), you create low level IMD with the reclocking frequency (50Hz and harmonics).

I suggest to make your PCB so that you can also use use 4...8FS DEM clocking.

Thor

I already made the DEM 50 hz with the last build , measurement were not that bad , you will find them at page 415 , as I said before the projects here are from John ECdesigns , I am the one who build not the one who create

every good advice from real experience is good to take for me :)

Zoran , if you have link , pics , graph , etc.. from your work i'll be happy the see and read them :)

bunch of guys have read this thread , no one gave any help to make the signed magnitude logic working , maybe because they are not that skilled and/or experienced


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Probably. As reclocking introduces a delay, always reclock everything together.

Never worked with that ("simultaneous mode"), so no comment.
Lots of good work Thorsten. My only comment would be to suggest that In reclocking everything and using simultaneous mode this could be considered as 1/2 NOS mode as all edges repeat at 1/2 frequency.

I also concur in suspecting that bipolar and cmos based DAC's are sonically different perhaps for the reasons you suggest, though not necessarily of sonic improvement one way or the other. Nevertheless I prefer the bipolar PCM63 over the the PCM1702 as well.
 
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Good I tried TS mode opperation with '40 and '41A too, and it was clearly better than in I2S mode (for '41A). Probably because latching is same for both ch, and stopped clock...
.
(If the frame is 64bit and word for conversion is 16 bits, in the I2S where BCK is constantly present, than we have (64-16)x2=96 more spikes and ground bounces in just one Fs cycle.)

TDA1541 has no ground bounce. It's not a CMOS IC.

If driven from true TTL logic noise injected from BCK etc. will be low too, it only becomes a problem if the driving logic 5V CMOS with high edge rate.

Thor
 
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off topic, I always prefered AD1862 to PCM63, finding the first more neutral with the material it played. Are those two chips not Cmos ?

For the moment, I find the TDA1541A having the edge (if S1 or late Taiwann) over the AD1862. But the setup is a llittle complex : USB to I2S with two R-Core secondary then I2S to I2S logic board from InCanada with electronic isolator then Fifo then reclocker : each with its onw secondary from another R-Core traffo, ultra low noise reg.
After the the fifo the Masterclock have again its own secondary from a C-Core with shared reg for the I2S to PCM board for simultaneous before the boards. All linked with uf-l wires with same impedance. Crysteck clock with my acrylic local decoupling trick.

PS of the TDA are thre independant secondaries with emitter follower from a zener plus TL431 (Pedja Rogic AYA2, not the double rail from the flag ship as suggested by Thorsten).

It blured an Audio Grande ESS flag chip from the musicians guys whom listebed to it. I can imagine there is a huge margin yet to go further. Humm I have to to plug my Mori Master Clock with SCCut crystal from Laptech but in a slow mode 5.xxx and 6.xxx (I am a red book listener due to the huge material collection)
 
off topic, I always prefered AD1862 to PCM63, finding the first more neutral with the material it played. Are those two chips not Cmos ?
IMG_20231217_032427.jpg


Answer, a bit of everything for AD1862.

I suspect (reading between the lines) the bitswitches are BICMOS with temperature compensation.

Meaning the pull up is bipolar NPN and the pull down is an N-Channel MOS.

PCM63? All sources are silent on the subject.

Thor
 
Pcm1702 is cmos version of pcm63, was stated somewhere if i recall right. So pcm63 is most probably bipolar in design.
I recall that too. Linn had a CD player that supported plugin "upgrades" of PCM63's to PCM1702's. After the upgrade of someones unit I was given the questionably inferior PCM63's that I personally preferred. In the listening the PCM1702's were arguably more natural, though they sounded more lossy of inner detail and sustain as I recall.
 
What about development of new dac chips that address the known issues?

Who would do that?

(I know, the industry seems to think it isn't worth it, either because of no significant advantages or no profit in it).

Precisely.

You have to make a discrete DAC. As we know, all the usual solution suck objectively.

So we need a new paradigm.

Say 16 bit thermometer DAC with for the top 4 MSB, using oversampling and (say) 11.xx/12.xx MHz update frequency. Can also act as DSD FIR DAC on demand should we need DSD.

Then an R2R DAC for the next 15 Bits (making it a 19bit Multibit DAC to here) and a low order DS Modulator at 256 FS for the faithful reproduction of of the analogue noise below bit 19 (bit 20 to 32), or off when we run DSD.

I would probably use a distinct set of drivers that allow a tristated output and run these as "RTO" at 75% duty cycle with deliberately doing any logic operations in the 25% of the time the DAC output is "open", so the output is not disturbed by any logic operations.

Needs a "Master of Dark Arts" FPGA Wizard to cooperate with me. I can do the hardware, I don't want to learn the FPGA equivalent of assembler at my age.

Thor
 
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Anyway it exists, and spikes to the +5Vdigial are even more present...

I have had opportunity to evaluate this with a number of TDA1541 based DAC's. All with TL431 based regulators (later versions use a Sziklai version) with a variety of "soft input" circuits on 2-4 layer PCB's and SMD decoupling below the TDA1541, I never encountered noise visible on a 300MHz 'scope at 1mV/DIV using homemade (well, lab made) differential probes.

Thor
 
In the datasheets:
input current pins (1, 2, 3 and 4)
digital inputs LOW Vi = 0.8 V

digital inputs HIGH Vi = 2.0 V
So, the amplitude of inputs should be in that range.
That mens that digital attenuation of the inputs has to be done...
(And that is for every DAC chip with off-course different values.)
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For the any other digital module prior to the attenuation
overshoot and undershoot has to be applied.
That is easy to check with measurements and with small pot find the right value of Rseries beetween EVERY out-to-input digital IC. (The values of R are different because of dif. Freq. even for the same ICs in line. Some members already try, measure and set the whole chain from the input to end and report in the topic. With sound and analog measurements benefits.)
like in this example.
https://electronics.stackexchange.c...undershoots-using-ferrite-beads-does-not-help
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Say 16 bit thermometer DAC with for the top 4 MSB
I am thinking about that for some time too
That is (2**4)-1=15 bits of thermometer transcoded of first 4 bits... :(
(for 5 bits to transcode to thermometer giving 31 bits, pretty un-obtainable, much complicated citcuit and giving too many delay to cope with...)
Only one configuration of logic ICs I found working (by simulation) and worth to try in praxis.
I can send You in a PP.
I will not use micro-controllers, CPLDs or any programmable device...
I don't want to learn the FPGA equivalent of assembler at my age.
Same for me, with paradox that I was long time ago in programming school. But that was almost 45 year ago.
Now I restrict to myself to use Matlab, Mathcad and very rare software for Arduino. That is all.
I am pretty sure that many older folks in the forum thinking the same.
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