Probably. As reclocking introduces a delay, always reclock everything together.
Never worked with that, so no comment.
Using attenuation and low-pass circuits removes the noise from the data/clock input.
The electronics themselves inside the TDA1541 are in effect ECL and should not work in saturation, except bit switches.
There are many options, among those I tried I liked the "balanced clock injection" with a fairly "soft" clock best.
Yes, I did.
Thor
For my limited experience, simultaneous mode option using the two pins for Data is giving more details on all the bandwidth. Very good in particular with late Taiwann 1541A chips. However in a different sounding style and signature I found an early S1 (single crown) in the same layout but this time in I2S mode and Fifo circuitry removed with just an Xmos USB to I2S was also very musical and good envelopment both for classical music.
But it is also maybe the simultaneous mode circuitry I use (IanCanada) had some alignement errors and in front of the Fifo, all with further supplies. Despite that It sounds more Studio on most of the music.
Just a two cents testimonie as it is not measurement related and subjective listening opinion in a particular hifi system.
What I discover hower is indeed the front end input treatment is critical to enhance the good qualities of this dac chip, that is staying my every day DAC (chip). At the end of his day, the simultaneous mode on Pedja's board is working good for me on my old 16/44 library. Of course I tweaked (for the best or the worst) a little with some John's ECDESIGNS work (his TDA1541A DACs are collector imo as well as the AMRs') and I hope when having a little more time to finish the I/V section of your termonic valve stage paper with an hybrid mu follower section from Moglia and a masterclock with Mori's SC-Cut crystal ! It migth be or not overkill for that chip, but I like the diyed cars in Tokyo Drift movie, so.... !
I am a non tech, I didn't understand the -15V of your design with the last section being common to the + 5V (biasing diode TL431 behavior?), anyway, it's cool to visit us ! (I expected a common -15V and -5V, but I didn't checked on the tDA 1541A shematic yet according your post above)
But it is also maybe the simultaneous mode circuitry I use (IanCanada) had some alignement errors and in front of the Fifo, all with further supplies. Despite that It sounds more Studio on most of the music.
Just a two cents testimonie as it is not measurement related and subjective listening opinion in a particular hifi system.
What I discover hower is indeed the front end input treatment is critical to enhance the good qualities of this dac chip, that is staying my every day DAC (chip). At the end of his day, the simultaneous mode on Pedja's board is working good for me on my old 16/44 library. Of course I tweaked (for the best or the worst) a little with some John's ECDESIGNS work (his TDA1541A DACs are collector imo as well as the AMRs') and I hope when having a little more time to finish the I/V section of your termonic valve stage paper with an hybrid mu follower section from Moglia and a masterclock with Mori's SC-Cut crystal ! It migth be or not overkill for that chip, but I like the diyed cars in Tokyo Drift movie, so.... !
I am a non tech, I didn't understand the -15V of your design with the last section being common to the + 5V (biasing diode TL431 behavior?), anyway, it's cool to visit us
! (I expected a common -15V and -5V, but I didn't checked on the tDA 1541A shematic yet according your post above)
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The arrangement for the -5 and -15V supplies, reminds of a direct cap between -5 and -15 pins that some people implement, but this is a bit different. I need to look at it ...more.
May you, please, share the output stage as per the AMR device, I am curious to see if it implements the same 'contact bias' as your E88CC circuit. I suspect not, given the detail in the schematic that was provided but I would really like to see what it looks like on paper.
May you, please, share the output stage as per the AMR device, I am curious to see if it implements the same 'contact bias' as your E88CC circuit. I suspect not, given the detail in the schematic that was provided but I would really like to see what it looks like on paper.
I am a non tech, I didn't understand the -15V of your design with the last section being common to the + 5V (biasing diode TL431 behavior?), anyway, it's cool to visit us
Actually, in a later DAC I used a separate PSU winding just for TDA1541, with TL431 set up as Zenner Chain, with CCS -> +5V -> 0V -> -5V -> -15V -> AC -CCS.
It makes sense when you remember kirchoffs law. In any circuit, at any time the sum of all currents in each and every node must be zero.
Together with "soft input's" avoiding throwing any noise into the IC, all currents in the TDA1541 are now confined to this loop with a single PSU isolated from anything else, only audio currents "escape" to the I/U conversion from where they must return to the "ground" pin of the TDA1541 (remember "Ground Isn't"*).
Thor
* The long version of "Ground Isn't (Ground)" is:
"Ground is a convenient fiction for a point with a fixed potential, in reality such a thing is more rare than your average unicorn or normal alien flying saucer, REAL "ground" is a dumping ground for all sorts of both waste and signal currents into a distinctly non zero impedance creating all sorts error voltages, that with injudicious layout cause error signals in the actual signal."
The pins layout of this chip is not easy, not like a PCM63 or an AD1862 I found for a basic diyer like I am.
I tried to draw something relative to what Pedja and John here made, but with a special direct and shortest autobahn isolated path between the the AGND & DGND for giving a chance to share the closest potential possible. For that I used some slicing to force the digital input pins to "see" first the DGND pin (not easy as the AGND is close to the I2S pinds. Then the analog output and 14 DEM as the 3 voltages to see faster the AGND like John and Pedja made from a long time. I just guessed high frequencies current are more travelling straigth and foccused VS the analog current. But was just a guess. I could have shared the AGND and DGND on a central island bellow the TDA chip, but I wondered if it was so good as all the 14 DEM are referenced there to make the shorted inductance betweens the 14 pins ans the ground.
Of course a plain layer ground had been possible too, but I found the "management of the 3 voltage pins and ground together, asked some care. After some try If ound from basic listening test experiment workingg with Pedja's 3 rails (each voltage has its own secondary from the trafo) than it was better to decouple locally only the -15V at its feet with a smd cap. Pedja seemed to like it (sounds fast and tigth with a bass that have more PRAT than the AD1862, lol , how is that possible, lol) btw with some other basic caps arengement I made which was zero decoupling after the emiter follower in his AYA2/4 circuitry.
Maybe I just added distorsion that sounded good, lol !
Edit : I also wondered if a total separation (isolation was possible on the pcb between the digital front end and the analog output, if AGND and DGND were shared together inside the chip. My basic non tech knowledge produced such strange thougths around this chip (drifting in circle at Shibuya between the zebra walkers cross paths.)
I tried to draw something relative to what Pedja and John here made, but with a special direct and shortest autobahn isolated path between the the AGND & DGND for giving a chance to share the closest potential possible. For that I used some slicing to force the digital input pins to "see" first the DGND pin (not easy as the AGND is close to the I2S pinds. Then the analog output and 14 DEM as the 3 voltages to see faster the AGND like John and Pedja made from a long time. I just guessed high frequencies current are more travelling straigth and foccused VS the analog current. But was just a guess. I could have shared the AGND and DGND on a central island bellow the TDA chip, but I wondered if it was so good as all the 14 DEM are referenced there to make the shorted inductance betweens the 14 pins ans the ground.
Of course a plain layer ground had been possible too, but I found the "management of the 3 voltage pins and ground together, asked some care. After some try If ound from basic listening test experiment workingg with Pedja's 3 rails (each voltage has its own secondary from the trafo) than it was better to decouple locally only the -15V at its feet with a smd cap. Pedja seemed to like it (sounds fast and tigth with a bass that have more PRAT than the AD1862, lol , how is that possible, lol) btw with some other basic caps arengement I made which was zero decoupling after the emiter follower in his AYA2/4 circuitry.
Maybe I just added distorsion that sounded good, lol !
Edit : I also wondered if a total separation (isolation was possible on the pcb between the digital front end and the analog output, if AGND and DGND were shared together inside the chip. My basic non tech knowledge produced such strange thougths around this chip (drifting in circle at Shibuya between the zebra walkers cross paths.)
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All the grounds are in the same time A and D. That is because the conversion happening in the module...
They are connected.
Maybe the best way is to "isolate" complete AD section in the way:
a. 2 power supply transformer secondaries well isolated. Each with C.T. and full wave rectifier. One for +-5V other for +-15V. Every C.T. is the "physical" ground and connected close to the DAC chip. This +15V is optional and could be used as PS for the buffer at analog side.
b. digial inputs are isolated (and recklocked after that). So the MCK chould be isolated too and 2 x of max BCK for highest Fs. Each line should have separate single isolator chip, followed by 2 x serial Flip Flop (could be in one chip package). Goal is to prevent interference with different F in same IC chip. So one isolator, one double F-F per digital line.
c. All digtal lines should, treat for signal integrity, (simple R in the signal path) to reduce spikes bigger than PS value, and also reduce ground bounces.
d. Attenuation at the input points in the range defined in the datasheet of Hi and Lo levels. (C and D will significantly reduce the HF noise, and that is crucial to implement IF the AD ground continuing galvanically un-isolated to pure analaog system after...)
...
e. Riv, or IV circuit is a part of AD section (not pure A section) and should be isolated with transformer. After that the signal is "pure analog"
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moved a bit e. from other points that could be tricky part, because of "mixing" AD section and A section...
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It is related to all DA sections not only for TDA's
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If I am not wrong, a) is done by Audial on shelf flagship DAC. But no CT, each secondary is floating: + 0 -
b) never seen that yet in a diy a pcb . only saw a standalone fifo chip
c) also works for reflections between the emitter and the load. although it is often at the output of the usb to i2s, it is not always seen in diy near the digital input of the chip. However I remember 25 years ago in a Philips CD723 I removed those resistor at the input of the tda1545A and more details was won w/o hearable distorsion or harschness againt all logic ?!
d) ok
e) : interresting, how to proceed ?
Wonder if most is going to Agnd . Never thougth to 3D wire the Dgnd pin to the Agnd pin by a wire above the dac chip far from the gound, this last only connect to the plain ground ! Well I do not know if it makes any difference at the end of the day.
b) never seen that yet in a diy a pcb . only saw a standalone fifo chip
c) also works for reflections between the emitter and the load. although it is often at the output of the usb to i2s, it is not always seen in diy near the digital input of the chip. However I remember 25 years ago in a Philips CD723 I removed those resistor at the input of the tda1545A and more details was won w/o hearable distorsion or harschness againt all logic ?!
d) ok
e) : interresting, how to proceed ?
Wonder if most is going to Agnd . Never thougth to 3D wire the Dgnd pin to the Agnd pin by a wire above the dac chip far from the gound, this last only connect to the plain ground ! Well I do not know if it makes any difference at the end of the day.
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Yes this is done by many diy-ers, maybe not published widely... I tried too.b) never seen that yet in a diy a pcb . only saw a standalone fifo chip
IF the attenuation prior to the inputs is aplied than no need for signal integrity "trimming" with serial Resistor. Signal integrity has to be applied by measurement and finding value of the resistor in each specific point, between the digital chips. The values are difefent because of the specific ICs and different F. But it is easy and could be done with scope and one small pot of 220ohm. From beguining the signal path to the end. End will be simple attenuation circuit in the range of Hi/Lo values
Yes
, there is just one way of how:one way is to use current injection (where needed) and Riv (in the range of specified offset). That is usually small values. And small voltage Vp-p. The R should be as many members evaluate - a non inductive (non - reactive in general, small C and L...)
That fact is implicating that after Riv should be better to apply a buffer as low capacitance input, high impedance input, non reactive load to the DAC with Riv end...
This buffer THEN can drive isolation transformer. With low signal value transformer will have very low distortion, and with low impedance buffer driver inductance of primary can be lower. So the less complicated transformer will act better. Buffer can be powered with +-15V from the AD side because it is before "real" analog side...
.
After that, on the secondary, comes "true analog" end. Then put the amplification stage with needed gain.
about phase:
On the Riv Voltage will be in opposite phase, buffers are usually are IN phase, so the secondary when used step up transformer, should be inverted for IN phase. More turns in secondary will significantly reflect with transformation ratio in the primary and load the buffer, that will have some impact even on the very low impedance of the buffer driving the transformer...
When used 1:1 isolation transformer, turns are lower capacitance transfer is 1, and persuming SE gain stage that inverts the signal, secondaru has to be in phase.
.
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Another way for the example is to use discrete IV, supplied with AD power branch
With again buffer. And transformer. But because of larger line signal say 2Vrms (5.62Vp-p)
the transformer should be from best quality, and even than some distortion will occure...
.
If You want to use Tube amplification stage, then IV converter should set to smaller value of converted Voltage signal. Again smaller voltage value, buffer...
With again buffer. And transformer. But because of larger line signal say 2Vrms (5.62Vp-p)
the transformer should be from best quality, and even than some distortion will occure...
.
If You want to use Tube amplification stage, then IV converter should set to smaller value of converted Voltage signal. Again smaller voltage value, buffer...
Zoran ( and some others ) , I suggest you to build a setup with all the things you said , test it , mesure it , listening to it and come here to report , there is nothing like the real world , and this is what we lack of here , people are writting and saying a lot of stuff , but in the end we do not see many things .....
I am about to build the last I2S to simultaneous version of John , including 50Hz DEM , passive I/V and a lot of he's thougts , pcb's are on their way , more to come
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I am about to build the last I2S to simultaneous version of John , including 50Hz DEM , passive I/V and a lot of he's thougts , pcb's are on their way , more to come
.
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To arrive at a correct solution, it is critical to define the problem correctly.
ALL DAC's today are CMOS Logic based. This creates very distinct problems, as compared to TTL/LSTTL or ECL logic based bipolar transistors.
Here is the problem....
This is the schematic of two basic CMOS logic building blocks, an unbuffered inverter and a NAND and a NOR gate:
These three structures are the most basic building blocks that make more complex logic structures. The size and resistance (and gate capacitance) of the Mosfets vary between different logic series but this is the basic stuff.
Here a graph illustrating the behaviour of an HC unbuffered inverter
You can see input vs. output voltage and current for a SINGLE inverter at 4.5V. Every time the inverter switches, there is a relatively large current spike, because at the "midpoint" both mosfets in the circuit conducta as one is not yet fully off and the other one is already a bit on.
Every CMOS IC's has many such inverters or comparable structures making up gates. Each of them, when changing state causes such a current spike. Each inverter or gate takes a certain amount of time to change state as the gate capacitance must be charged up and that takes more current that flows either from Vcc into the gate or out of the gate into Vss (actually, if we want to na..i about it, electron flows are actually the opposite of the current flows).
A single stage change in a complex logic IC will set off a cascade of state changes in each single logic block, creating a cacophonic sequence of current spikes in both the Vcc and Vss lines. The spikes are fast (nanoseconds) and once the IC achieves a new steady state the current in Vcc & Vss pin's becomes minimal. One critical point here is that all these spikes will shift the IC internal Vcc/Vss nodes and thus shift effective midpoint.
For CMOS logic, dealing with all of this is a major challenge.
BUT, TDA1541 is NOT CMOS. So all the thinking and "best practice" coming from decades of practice with CMOS are not very useful. Because a lot of the logic is differential and with the correct input signal non-saturating any current variation in the PSU/GND pin's is either output signal or the 3rd harmonic and up of whatever signal passes through the differentials, likely far down on the actual quiescent current.
Key "escape" points for signal/data dependent current are the supplies (NOT "GROUND"), audio out and DEM Pin's.
The best way of thinking of TDA1541 (and ECLogic) is actually as analogue circuits and mostly as differential ones.
IF (big IF) I were to design a DAC with TDA1541 today, it would look like this:
1) Two (or four) TDA1541 per channel, differential, simultaneous mode to get up to 384kHz and ~ 116dB SNR at digital zero
2) One TDA1541 per channel, differential for the 16 LSB's, suitable mixing into the main output.
3) Use C0G SMD cap's on all DEM Pin's, below the IC to a separate ground plane for each IC terminating to AGND. Use "full loop" shunt regulated PSU as discussed before, in this case probably split by channel (3-5 TDA1541 draw a lot of current).
4) PECL based reclocking and splitting of data into the differential feed to the MSB TDA1541 and into the LSB TDA1541, data delay for LSB TDA1541 in the CMOS logic
5) CMOS to PECL translators run on CMOS logic feed and we split grounds and supplies completely between the (CMOS) Logic and ECL/DAC sections. Back to back diodes to limit fault voltages between sections ground, but the drive is fully differential, so we can tolerate some DC or AC offset between the two sections. Galvanic Isolation could be applied in the CMOS domain but seems unnecessary.
6) Clocks run differential, ECL, differential discrete oscillator (Driscoll?) with switchable crystal for 44.1/48k base, pullable for PLL control in situations where the source clock is not synchronous to internal clock.
7) Differential I/U conversion using NPN bipolar transistors (biased for 0V at Emitter) forming a Szikai circuit with a P-Channel FET, tube output as hybrid "Super Linear Cathode Follower" (as per Alen Wright), servo biased for 0V, filtering between I/U conversion and output buffer as Sallen Key, including optional HF boost at 20k and 40k to correct the NOS droop...
Note, I did not go in detail into the CMOS side, it just has to work and be designed to spit out the correct signals and be designed according to best practice (read Mr. Ott).
Well, as said, that's what I would do. I guess that would be an AMR DA-77 and cost a mint, considering it needs 6 - 10 pcs TDA1541 and would likely be a 2-Chassis device (separate PSU).
Thor
Hi, Idont know... (look at the year of membership on the forum)
I have built most of theese things earlier. Based on thees experiences I am posting?
!?!? I read about this before. Are you sure?
Instead of averaging the error of the MSB's across time so that one sample ideally has four DEM periods (too fast is a problem), or totally randomising it (free running oscillator), you create low level IMD with the reclocking frequency (50Hz and harmonics).
I suggest to make your PCB so that you can also use use 4...8FS DEM clocking.
Thor