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Old 16th November 2010, 04:15 PM   #3521
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Hi Maurizio,

Quote:
I would like to run it in Simultaneous mode in a Philips 304..

Is it possible to use the DEM from ECDesign for this configuration..?

ECDesign...do you hava any comment or suggestion for me?

Yes, the DEM clock synchronizer circuit will work when using simultaneous mode. One can view the DEM (Dynamic Element Matching) circuit as a separate circuit that provides accurate current division for the 6 MSBs. It is not strictly necessary to have certain frequency relation with bit clock or word select to make it work.

Typical DEM frequency equals 200 KHz, limiting frequency equals 7 Mhz. I have tested applications running on 44.1 KHz DEM clock with 470nF decoupling caps.

You can experiment with bit clock and multiples of the bit clock for the DEM circuit.

With my setup, I achieved best results so far with both 2.8224 MHz bit and DEM clock.
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Old 16th November 2010, 04:56 PM   #3522
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Hi Ryssen,

Quote:
You made the pcbs to?
yes, I have been manufacturing and assembling my own PCBs for over 30 years now.

Next one up is the Cirlotron PCB. PCB design is almost completed, it's a rather large PCB (19 x 19cm) with 3 on-board transformers. I plan to complete a working prototype PCB this week.
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Old 16th November 2010, 05:17 PM   #3523
Bigun is offline Bigun  Canada
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Quote:
Originally Posted by -ecdesigns- View Post
Hi Bigun,I attached a diagram of the stepped attenuator concept (repost).
Hi, thanks very much - I was away the last week on business so just saw your reply to my question.

you explained it perfectly. I like it and it's got me thinking about using it or something similar in my own projects.

Did you consider adding capacitors across each of the diodes to reduce h.f. noise further ?
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Old 16th November 2010, 08:20 PM   #3524
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HI..

Thanks for your reply. I'm not so involved in digital..can you suggesto to me a configuration for it?

I would like to reclock the LE signal as in the posted scheme. May i use the MCK for the DEM?

Thanks again.

Maurizio
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Old 17th November 2010, 11:46 PM   #3525
fvale is offline fvale  Italy
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I'd like to try the syncronous reclocking and DEM clock as shown in post #3465 to my main cd player which uses the old TDA1540D DAC. It's a Revox B225 with TDA7030 (oversampling) IC removed and with a low jitter masterclock fitted. Original oscillator runs at 4.2336Mhz, so I had to use a 8.4672Mhz Tent low jitter followed by a 74hc74 to divide it by two. This clock and and all the 3 tensions feeding the DACs are separately and accurately implemented.

Can someone confirm this operation is possible?

I mainly have 3 doubts:

a) BCK frequency. I believe I should feed it at 1/4 of the master clock = 1.0584Mhz. If I remember correctly in the past I fed 1/4 masterclock (2.88Mhz) directly from the divider on a TDA1541, avoiding direct connection to the decoder IC (oversampling removed). This worked well. But I'm not sure if it can be done with the TDA1540 too.

b) DEM. This is something completely new to me. On the TDA1540 a 820pF capacitor is always used and datasheet reports a 160KHz typical frequency with it a minimum of 100KHz and a max. of 200KHz. I don't know if feeding the BCK through the 74AUC1G74 will generate a suitable signal.

c) as far as I can understand the master clock is fed to the BCK's 74AUC1G74 in order to syncronously reclock it together with WS and DATA lines. Is this right?

Thank you.

Last edited by fvale; 17th November 2010 at 11:55 PM.
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Old 18th November 2010, 06:53 AM   #3526
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Hi fvale,

Quote:
a) BCK frequency. I believe I should feed it at 1/4 of the master clock = 1.0584Mhz. If I remember correctly in the past I fed 1/4 masterclock (2.88Mhz) directly from the divider on a TDA1541, avoiding direct connection to the decoder IC (oversampling removed). This worked well. But I'm not sure if it can be done with the TDA1540 too.
TDA1540 is a 14 bit mono DAC with external DEM capacitor (pin 8 and 9). The DACs run in 4x oversampling (44,100 * 24 * 4 = 4.2336 MHz bit clock). With NOS the bit clock needs to be divided by 4 resulting in 1.0584 MHz.

Quote:
b) DEM. This is something completely new to me. On the TDA1540 a 820pF capacitor is always used and datasheet reports a 160KHz typical frequency with it a minimum of 100KHz and a max. of 200KHz. I don't know if feeding the BCK through the 74AUC1G74 will generate a suitable signal.
The DEM frequency limits (100 ... 200KHz) relate to 820pF external capacitor. It's not the absolute minimum or maximum usable DEM clock range.

I haven't tested the balanced DC-coupled DEM synchronizer on the TDA1540, it might need some adapting (resistor values). It is possible that the TDA1540 like the TDA1541A accepts much higher DEM clock rates. You can start with 176.4 KHz (bit clock divided by 6). Based on max. bit clock frequency (12 MHz) chip circuits should be fast enough to support 1.0584 MHz.

Quote:
c) as far as I can understand the master clock is fed to the BCK's 74AUC1G74 in order to syncronously reclock it together with WS and DATA lines. Is this right?
Yes, the 74AUC1G74 synchronously reclocks the 1.0584 MHz bit clock, and both flip-flop outputs (Q and /Q) are used for both, DEM synchronizer and TDA1540 bit clocks. LE and DATA signals of both TDA1540 chips also need to be synchronously reclocked for lowest jitter.
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Old 18th November 2010, 07:34 AM   #3527
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HI EC..

I post the schemes i would like to use..

One is from you..

Please..can you take a look to the other and tell me if is good for a 1541 also..?

In simultaneous mode..the DEM reclock need to created from the Master clock?

THanks...and sorry for my questions..but i've no experience in digital.

Maurizio.
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Old 20th November 2010, 08:58 AM   #3528
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Hi all,

Some project updates.

Seems I am coming close to my goal, TDA1541A-MK4 output stage was improved using power MOSFET current buffer, different bias resistors and an extra power supply filter to feed the bias circuit.
All 78XX / 79XX regulators were replaced with fast, high resolution discrete regulator modules. The hybrid coupling cap was also improved by using 2.2uF Monacor MKT, 3.3uF Monacor MKT, and 4u7 Intertechnik tin foil in parallel.

After these mods, the MK4 revealed flaws in my bridge power amp and ALPS volume pot.

The ALPS pot was replaced by a wire wound potentiometer that offers higher resolution and much better performance at lower volume settings.

I built a MOSFET Circlotron power amp to replace the MOSFET bridge power amp, using a breadboard setup for testing. This Circlotron amp uses 2 closely matched power MOSFETs for the differential input driver stage and two more for the Circlotron output stage. The design is fully balanced, this means that power supply noise and hum is effectively attenuated, resulting in no audible noise nor hum, thus maximum clarity. There are only 4 MOSFETs in the power amp signal path, offering very high resolution. The power amp was specifically designed to offer highest reliability and low power consumption. At average listening levels, one monoblock only consumes approx. 14 watts from the mains.

At this resolution, all parts become highly critical, meaning their effect on sound quality becomes clearly audible. I had to use non-inductive wire wound resistors for lowest noise. The conventional bridge rectifier also caused too much switching noise (even with Schottky diodes), so I had to use 3-stage stepped rectifiers. Finally the Circlotron power supply smoothing caps put their "signature" on the sound, introducing the next problem. This problem was fixed with a similar method as used with the hybrid coupling caps.

Yesterday I finally completed MOSFET Circlotron power amp PCB lay out and prototype, attached photograph shows the result. It's a single PCB power amplifier, PCB measures 19 x 19cm. The module offers 25 watts rms in 8 Ohms and has a total gain of 30x. The largest part of the PCB space is occupied by the input / driver stage stabilized power supply and both Circlotron output stage power supplies. Both Circlotron output stage power supplies have hybrid smoothing caps that greatly reduce the audible effect of particular electrolytic capacitor types. This results in attenuation of typical capacitor resonance peaks and offer very clean sound. There are multiturn trimmers for DC-offset (this power amp is fully DC-coupled), and bias current. The small transistor to the left of the power MOSFETs acts as a temperature sensor for thermal stabilization. The amplifier was designed such way that loss of power in one or more power supply sections doesn't lead to damaging amplifier nor connected speaker. The stabilized driver stage power supply and temperature sensor provide high bias current stability.
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Old 20th November 2010, 11:05 AM   #3529
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great work!
I wonder if you could post the latest TDA1541A output schematic using those power Mosfets and the value of bias resistors for experimental purposes only, Thanks
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Old 21st November 2010, 08:22 AM   #3530
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Hi luxury54

Quote:
I wonder if you could post the latest TDA1541A output schematic using those power Mosfets and the value of bias resistors for experimental purposes only, Thanks

Schematic is in post #3505.

I just added an extra filter between -15V and both 150K bias resistors.

The filter consists of 22 K Ohm and 10mH choke between -15V and both bias resistors. The junction of bias resistors is decoupled to GND using 470uF / 35V Panasonic FM cap. This filter attenuates noise from the -15V rail.

I now use discrete voltage regulators for +5V, -5V, and -15V.
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