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Old 15th October 2010, 01:13 AM   #3471
jstang is offline jstang  United States
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Hey MAxlorenz....

GOD BLESS THE MINERS AND THE RESPONSE TEAMS..... HIP HIP HOORAY.....
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Old 15th October 2010, 02:22 AM   #3472
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Location: osorno , Chile
...and the Government that never gave up!
We all learnt a few lessons with this tragedy...
A pity that at last the media transformed it into a quasi-circus.

Thank you on behalf of my humble country.
M.
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Old 15th October 2010, 03:15 AM   #3473
EUVL is offline EUVL  Europe
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> No it's quite different, I attached a concept schematic I am experimenting with.

Actually it is similar to the latest I am also working on -- a simple gain stage followed by a Circlotron Source Follower.

As shown, the output impedance in balanced mode is 2x (1/Yfs) of 2SK1530, which will be around 1 ohm at 2A bias. For me rather too high. I suggest you look into devices like 2SK3497, maybe 2x parallel at 1A bias each, per circlotron side.


Patrick
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Old 16th October 2010, 06:01 AM   #3474
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Hi maxlorenz,

I am also glad that the miners could be rescued, I followed developments on the news.
My grandfather worked in the Dutch State Mines. He died of lung cancer caused by exposure to coal dust.
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Old 16th October 2010, 06:21 AM   #3475
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Hi maxlorenz,

Quote:
I still think that power regulation/ripple rejection (and probably sound quality) could be improved on the different sections of the circlotron...but that is only a guess
Differential stages offer good PSRR, same with bridge output stages like the Circlotron. Power supply ripple and noise appears on both speaker outputs, and are rejected. The input / driver stage that already offers good PSRR is powered by a clean stabilized power supply. The input / driver stage only requires very little current (approx. 17mA), this also keeps ripple voltage very low. The input / driver stage also contains a hybrid choke (consists of multiple chokes and ferrite beads in series) in order to attenuate power supply noise and offer high impedance.

The H-bridge in my previous design also offered good PSRR but had the disadvantage of higher output impedance (2 powerFETs in series with the load), matching problems between N and P power FETs, and the need for two extra semiconductors in the signal path.
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Old 16th October 2010, 02:08 PM   #3476
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Hi ECdesigns,

Thank you.

Quote:
My grandfather worked in the Dutch State Mines. He died of lung cancer caused by exposure to coal dust.
Sorry to hear...it always amaze me how each human being is faced to confront one (his own) "path of experience"...and how groups of human beings share more or less one common "path".

Quote:
Differential stages offer good PSRR, same with bridge output stages like the Circlotron. Power supply ripple and noise appears on both speaker outputs, and are rejected. The input / driver stage that already offers good PSRR is powered by a clean stabilized power supply. The input / driver stage only requires very little current (approx. 17mA), this also keeps ripple voltage very low. The input / driver stage also contains a hybrid choke (consists of multiple chokes and ferrite beads in series) in order to attenuate power supply noise and offer high impedance.
Very clever. It is good to use free advantages of nature..yet, cleaner rails won't hurt, I guess...I mean, as a DIYer, we always want to give a personal touch. (even if an experiment)

Best of wishes.
M.
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Old 16th October 2010, 05:11 PM   #3477
jstang is offline jstang  United States
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Last post off topic for me....

But the strange thing about Black Lung... Its not the coal dust that causes cancer. Its the Radon particles that attach themselves to the Coal Dust that causes the cancer once the dust in the lungs. I have studied the affects of radon ( radiation ) on high density Memory Chips.....Can you say "blue screen" and parity errors.....


BACK ON TOPIC....

ECDesigns

Are you still mainly a 16bit/44.1 person...? I am about to head into the HD world mainly for the improvements in the time domain.

Although, I still love my linear interpolation 1541 DAC ( 9$ CDs from a local store ) .....it will be interesting to see which captures my ear in the end.

jk


Quote:
Originally Posted by -ecdesigns- View Post
Hi maxlorenz,

I am also glad that the miners could be rescued, I followed developments on the news.
My grandfather worked in the Dutch State Mines. He died of lung cancer caused by exposure to coal dust.
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Old 17th October 2010, 11:16 AM   #3478
Sandor is offline Sandor  Italy
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Quote:
Originally Posted by -ecdesigns- View Post
After extensive (listening) tests and feedback from critical listeners, I decided the TDA1541A-MK4 will be the final single-TDA1541A DAC version.


I attached schematic diagram of the MK4.
Thanks a lot for publishing the schematic. I'd like to use your reclock and dem circuits in my NOS dac. I only have the WS, BCK and DATA out of a CS8412 (used in master mode). No master clock is used, as I cannot send it back to the source. The clock out of the receiver is 2.8224 MHz.

1) 2.8224 MHz is maybe too high a frequency for the DEM synchronizer. Driving the CK input of U7 with the serial bit clock from the receiver and connecting Q and D together, I obtain 1.412 MHz out of the flip-flop. May I drive the BCK input of the TDA1541A with this signal?

2) Since I do not use a master clock, is there a point in re-clocking WS and DATA?

3) Which is the role of those anti-parallel diodes?

Regards.
Paul

Last edited by Sandor; 17th October 2010 at 11:30 AM.
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Old 17th October 2010, 07:34 PM   #3479
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Hi Sandor,

Quote:
1) 2.8224 MHz is maybe too high a frequency for the DEM synchronizer. Driving the CK input of U7 with the serial bit clock from the receiver and connecting Q and D together, I obtain 1.412 MHz out of the flip-flop. May I drive the BCK input of the TDA1541A with this signal?
BCK needs to remain 2.8224 MHz. DEM clock can be derived from BCK by using a divider, connect /Q to D input.

Quote:
2) Since I do not use a master clock, is there a point in re-clocking WS and DATA?
Without reclocking you will have 200ps MCK jitter (CS8412) plus SPDIF interlink plus source jitter. Without an ultra low jitter masterclock that shares the same time domain as the source, you will have no suitable clock signal for synchronous reclocking.

Quote:
3) Which is the role of those anti-parallel diodes?
D flip-flop Q output = "1", and /Q output = "0", first diode conducts, output voltage equals 2.4 - 0.6 = 1.8V.
D flip-flop Q output = "0", and /Q output = "1", second diode conducts, pulling output low, however the 1K resistor connected to /Q feeds current through D2, so output voltage now equals diode saturation voltage of 0.6V.

The diodes, together with the 1K resistor connected to /Q create an attenuated I2S signal that swings between 0.6V and 1.8V. The TDA154x I2S input threshold voltage lies exactly in the center (1.2V).

This forms a simple, highly effective, and very reliable I2S attenuator.
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Old 17th October 2010, 08:14 PM   #3480
Sandor is offline Sandor  Italy
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Default I2S attenuator

Hi ecdesigns,
thanks a lot for your reply.
Your I2S attenuator is a very clever circuit. Willing to implement this attenuator, even in absence of a master clock, I could use U5 and U6 all the same. The options for driving CP are:
1) using the 2.8224 Mhz signal from the receiver (pin 12 of the CS8412),
2) using the 1.4112 MHz signal out of the divider or
3) using the 11.2896 MHz signal out of pin 18 of the CS8412

Which option is best? Or should I better use a different attenuator?
Regards.

Paul

Last edited by Sandor; 17th October 2010 at 08:22 PM.
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