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Old 25th March 2009, 10:34 AM   #2731
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Default ps decoupling on tda1541 pcb

Hi John,

on the tda1541 pcbs, there are 2 x 33uf bypass caps for each of the 3 voltages. I am about to order all of the components for this project - is it worth ordering different values caps and more of them so that i can add them to the pcb, or am i better off sticking with the 33uf bypass caps and try to add some extra smd bypass caps to get up to the 1000uf value that gave the best performance.
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Old 25th March 2009, 03:32 PM   #2732
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Hi John,

Have you tried those SMD polyphenylene sulfide caps for the decoupling of the tda1541? I recall reading that both Pedja and Thorsten have gravitated to these with their current tda1541 based players.
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Old 25th March 2009, 03:58 PM   #2733
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Hi scrutinizer,

Quote:
I was just curious about how this machine would sound in NOS operation, but after desolder de SAA7220 p/b and reconstruct it's I2S lines ... listening to it reveals noise that drifts in en out of signal.
Could you email me a higher resolution schematic, including the TDA1541 chips and output circuit?

SAA7220 pin 2 (clock input) doesn't seem to receive a clock signal, so when connecting the bit clock input of the TDA1541A to this pin, it won't work. This is probably part of the multiple sample frequency support. Also connect a 2K2 pull-up resistor between SAA7220 pin 2 and Vcc (the removed SAA7220 has an internal pull-up on this pin).

I suggest dividing the crystal clock input signal (SAA7220 pin 11) by 4 using a suitable divider like a 74HC161. Then feed the divided clock signal to the TDA1541 bit clock input.
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Old 25th March 2009, 05:16 PM   #2734
ccschua is offline ccschua  Malaysia
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With regards to the transimpedance circuit for TDA1541a, I found replacing the output resistor (after the 4.7uF cap) to different can alter the sound.

At first I use 8k, found less mid but clear high and low. When I change to 150k, the mid is more pronounce. Is it the 8k and the 4.7uF roll off at too high a frequency ?

I notice no matter what I do, the dc offset at the output is minimum 5mV. Is it the 4.7uF pp cap not good ? leaking ?

Hi Luxury54, how is it your TDA1541a doing. Are u trying the floating charge transfer ? I may be thinking to replace the output coupling cap with Mundorf ZN.
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Old 25th March 2009, 05:48 PM   #2735
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hello ccschua,
I'm modding a Marantz player based on TDA1541A now and regarding decoupling capacitors i must say that i found
out a strange thing in a positive way !
The player had originally 14 pieces of 100nF SMD capacitors under the DAC for decoupling and i bypassed them all with 220nF Wima film and the sound wasn't so impressive at that time...
But just doing an experiment and decoupling the last MSB pin with 1uF tantal capacitor and the one near it with 220nF also tantal gave me the sound i was never hoping to obtain just by these capacitor decoupling tweaks

The bass became deeper and softer,the highs became very crisp and there is a slight attenuation of the middle-high range compared to the non polarized film decoupling caps
I love the new sound these caps gave me
Just try it yourself you'll be surprized, but remember since tantal capacitors are polarized and we are dealing with -15V here, you have to solder them with + side to earth and - to TDA pin.
I think i will desolder all of the films and SMD and go with short leg 100nF tantal all the way

ps.
I saw in many schematics/equipment and i don't know if it's a rule,but in general the modules that were powered simultaneously by + and - power rails were always coupled with non-polarized film caps ,and the modules where just one positive power rail was present were always (de)coupled with polarized caps...having this in mind and since only -15V is used in TDA as for this analog part ,i experimented here with polarized tantals and found out that are just great!
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Old 25th March 2009, 08:14 PM   #2736
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Quote:
Originally posted by soundcheck
It seems that you're still improving, looking at the recent capacitor discussions.

I used to use a Thel Silver Mica (0,1u) as coupling cap some time ago. It is really close to a piece of wire. (I tried also some other high-end caps - all of them failed in comparision.)

If we talk about ultimate solutions: I am running my Sabre DAC "without coupling caps" directly connected to the amp right now. You'd be surprised. The best cap is no cap! ( beside that you'll save a hell lot of money)

Cheers
I am building one of Johns 4 x TDA1541 DACS, and am thinking about the best i/v stage. I have been thinking about using Vishay Z foil resistors for the RIV - and even considering those 2 or 3uf V-CAPS - i must be mad at that price, so a balanced output from the DAC certainly appeals.

Does anyone have any schematics/ details regarding the trans impedance/ I/V stage for the 4 x TDA1541 DAC, WITH balanced output? please?

Brad
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Old 25th March 2009, 08:31 PM   #2737
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Quote:
Originally posted by -ecdesigns-
Hi scrutinizer,



Could you email me a higher resolution schematic, including the TDA1541 chips and output circuit?

SAA7220 pin 2 (clock input) doesn't seem to receive a clock signal, so when connecting the bit clock input of the TDA1541A to this pin, it won't work. This is probably part of the multiple sample frequency support. Also connect a 2K2 pull-up resistor between SAA7220 pin 2 and Vcc (the removed SAA7220 has an internal pull-up on this pin).

I suggest dividing the crystal clock input signal (SAA7220 pin 11) by 4 using a suitable divider like a 74HC161. Then feed the divided clock signal to the TDA1541 bit clock input.
Hi John,

Thanks for your time and advice!

I found the culprit, John ..... One of the opto-couplers sending word select to the TDA1541a/S1 was unstable due to a 'old' solder joint gone bad over time.
After reparing and tweaking the lowpass .... the sound was not bad at all from this oldtimer.

I possess also the CD 94, maybe it's a nice idea to turn that into a transport only (cdm 1), providing I2S to the CDA 94........

rgds,

Anton.
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Old 25th March 2009, 10:29 PM   #2738
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Hi luxury54,

Quote:
I think i will desolder all of the films and SMD and go with short leg 100nF tantal all the way
TDA1541A LSB current change equals 0.004 / 65536 = 61nA.

Active divider decoupling caps are directly connected between divider output and GND, so the slightest decoupling cap leakage current will change exact output current of 6 MSBs!

Typical tantalium cap leakage current (0.1uF ... 1uF) equals 500nA, so this will introduce up to 3-bit error on each of the MSBs. Leakage current also changes with other external factors like temperature and voltage. The tantalium caps should be ok for power supply decoupling.

Ceramic capacitors are microphonic (they will produce a small voltage when tapped, and will flex when a voltage is applied). High-K ceramic caps can produce audible sound when driven by a bias voltage with a super-imposed 1KHz sinewave for example. This makes them less suitable for audio applications.

Quote:
The bass became deeper and softer,the highs became very crisp and there is a slight attenuation of the middle-high range compared to the non polarized film decoupling caps
The active divider decoupling caps do have clearly audible effect on sound quality. The decoupling caps need to have low inductance, very low leakage current, and low microphonics. Some of the active divider outputs have only half the ripple frequency (check TDA1540 datasheet), and the ripple currents vary with the output current.

So capacitors filtering fDEM / 2 need to have twice the capacity of the capacitor filtering fDEM. fDEM is typically around 200 KHz. Capacitors filtering lower currents also have lower ripple current to filter, so capacitance can also be lower. When selecting capacitor values with respect to DEM clock ripple current frequency and active divider output current, and using 1uF as maximum value, following would apply:

pin 13,18, 2mA, fDEM /2, 1uF
pin 12,19, 1mA, fDEM, half current (13,18), twice the frequency of MSB, 250nF
pin 11,20, 0.5mA, fDEM / 2, half frequency, half current (12,19), 125nF
pin 10,21, 0.25mA, fDEM, half current double frequency (11,20), 31.25nF
pin 9,22, 0.125mA, fDEM / 2, half current, half frequency (10,21), 31.25nF
pin 8,23, 0.0625mA, fDEM, half current (9,22), 7,8nF
pin 7,24, 0.0625mA, fDEM, equal current (8,23), 7.8nF.

In practice, 1uF (MSB), 220nF, 120nF, 33nF, 33nF, 8.2nF, 8.2nF. This would give equal ripple currents on all MSBs.

Active divider decoupling also depends on DEM clock. Like mentioned before, DEM clock oscillator is able to "lock" on (on-chip) BCK crosstalk. By selecting DEM clock capacitor values that produce (almost) exact multiples of fs, the DEM clock will "lock" to BCK and jitter amplitude would drop significantly. The often used 470pF and 680pF won't result in a "lock" and produce maximum DEM clock jitter amplitude.

Here are some capacitor values that result in a "lock" condition, capacitance might vary slightly due to TDA1541A tolerances:

235.2 KHz, 350pF
256.58181 KHz, 318pF
282.24 KHz, 300pF
313.6 KHz, 260pF
352.8 KHz, 250pF
403.2 KHz, 203pF
470.4 KHz, 180pF
564.48 KHz, 145pF
705.6 KHz, 122pF

The capacitors need to have tight tolerance (1%).

Today I tested a new (more stable) external DEM clock circuit. It consists of a differential TTL-level clock source (352.8 or 705.6 KHz), and 4 resistors. each DEM clock pin (16 & 17) is connected to -15V through a 2K2 resistor. The TTL-level clock signals are connected to pin 16 & 17 using 10K Ohm series resistors. The resistors will provide bias voltage (prevents the internal DEM clock from oscillating), attenuation and level conversion. This is the best performing DEM clock circuit so far.

DEM clock operation must be tested with low level recordings (-40dB for example). Sheffield test CD "My Disc" contains such test tracks. When the DEM clock doesn't work, there is huge distortion, if it has spurious oscillations (usually around 7 MHz) sound quality will vary, but won't be optimal. Correct working DEM clock should produce a crystal clear sound. The fact that clock signals are measured on both pin 16 and 17 doesn't mean that the on-chip DEM clock oscillator actually functions. It can simply stop (no clock signal), or oscillate at different (higher) frequency.


Quote:
and since only -15V is used in TDA as for this analog part
Unfortunately not, both +5V and -5V are also used for analogue circuits, in fact both +5V and -5V appear to be most critical. I had best results with approx. 3000uF (multiple caps in parallel) for power supply decoupling (TDA1541A).
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Old 26th March 2009, 04:42 AM   #2739
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thanks for the precious info ecdesigns,
so instead of building the differential 352khz DEM clock (derived from masterclock) is it worth to try with only one 250 pF quality cap that will lock on 352.8 khz on DEM pins (16,17)?
Is there big difference in sound using these two options compared to each other?
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Old 26th March 2009, 07:02 AM   #2740
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Hi luxury54,

Quote:
so instead of building the differential 352khz DEM clock (derived from master clock) is it worth to try with only one 250 pF quality cap that will lock on 352.8 KHz on DEM pins (16,17)?
Is there big difference in sound using these two options compared to each other?
Tuning the capacitor is the easiest way for lowering DEM clock jitter amplitude, but jitter won't be as low as with an low jitter external DEM clock (DEM clock oscillator intrinsic jitter). So this modification improves sound quality over the 470 or 680pF, but still isn't optimal.

I attached the schematic of a DEM clock oscillator & attached shift-register that's probably used in the TDA1541A (Source, IEEE journal of solid state circuits, vol. SC-14, No. 3, June 1979).

The external DEM clock capacitor is marked in red. The outputs A, B, C, and D are the shift-register outputs for driving the electronic switches of the active current dividers. The outputs change in a certain pattern in order to average between the output currents of the passive divider that is part of the active divider. The end result is 4 closely matched output currents, derived from 4 passive output currents (passive current divider) that have certain tolerances and aren't fully matched.

When the DEM clock capacitor is removed, the DEM clock oscillator will run on stray capacitance (few pF), and produces a clock signal of around 7 MHz. By removing the capacitor and connecting these terminals to -V (-15V), using 2K2 resistors, oscillation stops. Now the external clock signal can be injected through 2 x 10 K Ohm, basically toggling the oscillator circuit with the external 352.8 KHz differential DEM clock that is derived from the low jitter master clock.

Without the 2K2 resistors, the DEM clock may produce unwanted spurious oscillations (short bursts of 7MHz clock signals), or may become unstable and stops. This is why DI4T performance kept varying. I plan to modify the D4T soon, and am very curious how this will affect performance.

TDA1543 doesn't require a DEM clock as it only contains passive current dividers, so this DEM clock "problem" doesn't occur with this chip.
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