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#2501 |
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diyAudio Member
Join Date: May 2008
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referring to the photo below
![]() For U1, Q0 = Q1 Q1 = Q2 Q3 = Q4 .... so on. the drawing use a different convention. I will use Q1 convention (instead of Q0) Since CS8412 is doing 4 times, I need to get CS8412 in NOS. to get to 4x oversampling, I bent pin 9 (Q1) and short pcb pin socket pin 9 (Q1) to pin 7 (Q2). Q2 = 2.82 MHz. Which means U4 CS 8412 FCK is receiving the 2.82MHz instead of 5.64MHz. Is this correct ? |
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#2502 |
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diyAudio Member
Join Date: May 2006
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Hi ccschua,
FCK (pin13) can be used for connecting an optional 6.144 MHz external clock for providing information about source sample rate. So the 5.6488 MHz clock used here doesn't comply with the specs in the data sheet. I don't use this FCK pin and connected it to GND so it won't pick-up interference. X1 runs at 11.2896 MHz (4 x bit clock). The actual bit clock (for NOS) is at U1 pin 7 (2.8244 MHz). The word clock is available at U1 pin 13 (11.2896 MHz / 256 = 44.1 KHz). So when the SAA7220 is bypassed, the DAC already runs in NOS mode (2.8224 MHz bit clock and 44.1 KHz sample rate). |
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#2503 |
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diyAudio Member
Join Date: Jul 2004
Location: Texas
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Seems like years since this thread started. We like to see the finished product....Pretty Please
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#2504 | |
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diyAudio Member
Join Date: Dec 2008
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Quote:
reffering to that dac kit,the Hong Kong seller from ebay wrote it's specifications to be 8x oversampling,please check this link with also schematic included http://cgi.ebay.com/Hi-End-CD-DAC-TD...742.m153.l1262 "SPECIFICATION 1. 16 bit DAC for Hi-Fi Audio 2. S/N can attain 110dB 3. 8x oversampling frequency" so my question would be,where from does he obtain a 2x oversampling in case we leave saa7220 in place (that does the 4x oversampling) also check Doede's dac using a simillar reclocking circuit,he is grounding pin 13 on CS8414 just like you said ![]() ps. sorry to polute your original thread with these kind of questions |
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#2505 | |
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diyAudio Member
Join Date: May 2006
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Hi MGH,
Quote:
It IS years since I started this thread on May 12, 2006. This thread illustrates how difficult it is to design a high-performance DAC. At the end of 2008, all previous developments started to produce a clearer picture of the problems involved. Next, each problem was systematically tackled, and most significant progress was made. Just when I assumed that the highly optimized (and also rather complicated) DI4T would be the "ultimate NOS DAC", and it would only be a matter of designing the final PCBs for it, the unexpected happened. The simple breadboard test set-up that was used for testing the new DI4T modules, sounded rather good. The "problem" was that the test set-up had a single TDA1543 DAC chip. Comparison with the DI4T reference DAC left me baffled, there was little audible difference. It was a rather frustrating experience after all the hard work put into DI4T design and tuning. The messy breadboard test set-up evolved to the messy D1M prototype. Maximum performance was squeezed out of the TDA1543 chip by using a low jitter masterclock / tracker module, a new high-performance trans-impedance I/V converter / buffer, and low noise shunt regulators. The D1M now clearly performs much better than the DI4T reference DAC. So why not go for the much simpler, cheaper design that offers even better sound quality than my DI4T reference DAC? |
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#2506 |
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diyAudio Member
Join Date: Dec 2008
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hmmm,not many people, especially design engineers that perform a business selling hi-fi equipment, would tell the truth to their customers about cheaper better sounding devices,...their marketing policy is to sell the most expensive devices with most profit even if it is a bullsh*t (generally speaking,i was not reffering to your better,more expensive product here)
so,not as if it would matter,but ecdesigns gets my whole appreciation for his remarks !
__________________
== NIHIL SINE DEO - Nothing Without GOD == |
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#2507 | |
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diyAudio Member
Join Date: May 2008
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Quote:
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#2508 | |
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diyAudio Member
Join Date: May 2006
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Hi luxury54,
Quote:
TDA1541A data sheet specifies max. bit clock frequency (fBCK) of 6.4 MHz (TDA1541A data sheet page 2), this prevents using OS rates higher than 4x using I2S (time multiplex mode). SAA7220 data sheet specifies: The filtered data is output in I2S format at 5.6448 MHz bit rate, and a sample rate of 176.4 KHz (SAA7220 data sheet page 7). The resulting OS factor would be 176,400 / 44,100 = 4x. The TDA1541A can run at 8x OS when using simultaneous mode (pin 27 connected to -5V, TDA1541A data sheet page 5). Now data for both L and R channel can be clocked-in simultaneously, requiring only 16 bit clock pulses instead of 32. This would effectively double the amount of samples that can be clocked-in while staying below specified 6.4 MHz bit clock. The sample rate will then be: 5,644,800 / 44,100 / 16 = 8x. This is also the max. sample rate for a single TDA1541A chip. |
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#2509 |
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diyAudio Member
Join Date: May 2008
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I never learn this in university, but the audio university.
All this while, I thought I was running at 8x which is printed at the manufacturer website. I am totally wrong. So it sounds like tda1541a running in 4x is quite balance. To do 8x, I need to bend pin 27 of TDA1541a and solder it to -5V. Then can I know how to connect the SAA 7220 to TDA1541a ? I need to use DOBM to output 32bit word to pin 3 and pin 4 ? any other changes as per the schematic. |
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#2510 |
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diyAudio Member
Join Date: Sep 2006
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Hi John,
I was waiting for the arrival of the DI4. Have been hunting for the 1541s & now this post. Hmmm. Hey, maybe single 1541 would sound better then the 1543. Have you tried it ? Thanks |
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