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Building the ultimate NOS DAC using TDA1541A
Building the ultimate NOS DAC using TDA1541A
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Old 4th July 2007, 10:24 PM   #1601
Tazzz is offline Tazzz
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Default Re: TDA1541A DEM clock frequency / decoupling cap value

Quote:
Originally posted by -ecdesigns-

The DA1541A modules with the new smaller heatsink can accomodate 0.68uF decoupling caps. This is possible by placing half of the caps on the component side, the other half on the solder side (there is plenty of room underneath the modules). The 1 uF for MSB could be increased to 2.2uF if desired.

That should be more than sufficient to get very low ripple current on all active divider outputs.
I for one would be extremely interested on some scopecaptures of the waveforms on these pins with regard to capacitance values and DEM frequency.
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Old 5th July 2007, 08:33 AM   #1602
ecdesigns is offline ecdesigns  Netherlands
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Hi maxlorenz,

Thanks for your reply [post #1599]

Quote:
I confess that I had not see before your excellent and very detailed assembly instructions at your "downloads" page. Wow.
Yes making these vector drawings took a lot of time, but I wanted to make the assembly instructions as clear as possible. I still have to add detailed cable assembly drawings.


Quote:
I wait some R to begin with the DI8*4 project. This time I will take my time. Don't expect objectivity from my part with this one
Yes, it's best to take your time for this project. In order to create some more space for the heatsinks of the stacked TDA1543 chips, you could mount both REF resistors and multilayer decoupling caps on the solder side.

Only 8 REF resistors will be used now, if you plan to use higher REF resistor values, use 22 K Ohm with 10uF decoupling cap.

When completed, I am very curious about the comparison between both the DI 16 you already built, and the one with the 8 x 3 configuration.
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Old 5th July 2007, 09:11 AM   #1603
ecdesigns is offline ecdesigns  Netherlands
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Hi Brent Welke,

Thanks for your reply [post # 1600]


The scope must be able to resolve phase deviations in the picosecond range, so a large bandwidth oscilloscope (40...100 MHz) is preferred.

Make sure you have a low jitter SMD 48 MHz oscillator module, check the datasheet.

I now use a 48 MHz master clock oscillator based on a selected 16 MHz crystal and a WF10192. The 2.2 uF tantalium decoupling cap is soldered very close to the WF10192 power supply pins. The traces between crystal and the WF10192 are very short as well. There is a 2.7 K Ohm resistor in parallel with the crystal. The crystal oscillates on the third overtone.

The module only has a few parts and is quite easy to construct. I added a photograph of the module I experimented with, so soldering is very messy. The PCB is single sided.
Attached Images
File Type: jpg 48mhz.jpg (23.8 KB, 1861 views)
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Old 5th July 2007, 11:12 AM   #1604
lcsaszar is offline lcsaszar  Hungary
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Default DEM clock

I tried the DEM clock -ecdesigns- suggested (pin 16 of TDA1541A driven through a small capacitor, pin 17 connected to GND through 100 nF). Then searching the web I found the internal DEM circuit is most likely an emitter-coupled symmetrical multivibrator, and I modified the DEM drive circuit:

I divide my master clock of 4.2336 MHz by 6 with a 74HCT163 sync divider with 74LS00 feedback, this results in 705.6 kHz. This in turn is didided by 2 with a 74S74 D-flipflop. I couple both the inverting and non-inverting outputs to pin 16 and pin 17, respectively through 470 pF capacitors. The TTL-level squarewave is an overload at the DEM inputs, but no harm so far.

In the next step I will try 705.6 kHz (4.2336 MHz divided by 6, resulting in 16 DEM clock cycles per sample) or perhaps 529.2 kHz (4.2336 MHz divided by 8, resulting in 12 DEM clock cycles per sample). In the last version only 2 x 74S74 is necessary, and I can synchronize the DEM clock to the master clock by using the last flipflop that provides the opposite phase DEM clock signals.
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Old 5th July 2007, 08:14 PM   #1605
lcsaszar is offline lcsaszar  Hungary
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I tried the 529.2 kHz DEM clock version, and in a quick listening it works great.
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Old 5th July 2007, 08:58 PM   #1606
maxlorenz is offline maxlorenz  Chile
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Hi -ecdesigns-
Thanks for your tips.

Quote:
In order to create some more space for the heatsinks of the stacked TDA1543 chips, you could mount both REF resistors and multilayer decoupling caps on the solder side.
That was my plan from the beginning. Plus vertical mounting of the PCB for better convective cooling...

Quote:
Only 8 REF resistors will be used now, if you plan to use higher REF resistor values, use 22 K Ohm with 10uF decoupling cap.
Uf! I already bought 45K resistors for Rref. Too high?
Instead of multilayer I have Epcos polypropilene 100nF. I also have 10nf that I could parallel to them and see how it sounds...

As for the comparison, I am biased beforehand
I have enough chips to build two DI8*4 TDA1543 DACs
thanks to another beloved forum mate
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Old 6th July 2007, 10:32 PM   #1607
dddac is offline dddac  Germany
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Building the ultimate NOS DAC using TDA1541A
Quote:
Originally posted by maxlorenz

I have enough chips to build two DI8*4 TDA1543 DACs
thanks to another beloved forum mate







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Happy listening and building
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Old 7th July 2007, 08:55 AM   #1608
tubee is offline tubee  Netherlands
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Quote:
Originally posted by -ecdesigns-

The scope must be able to resolve phase deviations in the picosecond range, so a large bandwidth oscilloscope (40...100 MHz) is preferred.
I managed to check an buffered output of diy 27Mhz clock for jitter with a humble but here available 20 Mhz scope, the signal is finer visible on the screen, on cristal itself the signal is more blurry. I even managed to look 36mhz with this scope.
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Old 25th July 2007, 11:18 AM   #1609
MGH is offline MGH  United States
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Question Has anyone built or heard the DI8M DAC yet?

It's an expensive kit, and I would like some info on it's sonics. I know EC has described it in detail but I would like to hear from an impartial listener. I already have TDA1541As, just need the kit.
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Old 25th July 2007, 01:54 PM   #1610
Terry Demol is offline Terry Demol  Australia
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Quote:
Originally posted by -ecdesigns-
Hi oshifis,

I already tested 74H..74 chips, they had the worst jitter specs from all D flip-flops I tested, so I don't use them anymore. Using 2 D flip-flops in the same housing for different frequencies causes crosstalk and should be avoided. Unused INPUTS should always be connected to a steady signal level (GND). I got lowest jitter using D flip-flops from 74HC164 and 74F164 shift registers, that's why I use them a lot for timing critical circuits. The lower jitter is probably caused by the chip internal circuit architecture.

The 74xx161 is a synchronous divider. This means that the outputs change state fully synchronous with the input clock signal (BCK). The 74HC161 triggers on the positive going edge of BCK, this means that 74HC161 outputs also change on the positive going edge of BCK. The jitter at the divider outputs is very low (comparable to 74HC164), reclocking it with a 74..74 would actually increase jitter.
Hi EC,

How did you measure the jitter of the 74HC74 FF's? The jitter
induced by one of these, if correctly decoupled, should be very low.

Why do figure the shift register of same logic family - say HC, has
lower jitter?

cheers

Terry
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