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Old 31st May 2007, 05:20 PM   #1521
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Hi arielpuri,

Thanks for your reply,


Quote:
What sonic difference is now, between DI8 and DI16 DAC?
Is it big?

DI16 has 256x resolution, but DI8s TDA1541 has lower distortions.

That is not clear for me.

According to the people that already came over to listen to both DI DACs, the DI 8(M) sounds best, especially after the latest DEM clock mod. So I used the DI 8(M) as reference for the DI 16, and tried to match DI 16 sound quality to the DI 8M as closely as possible.

After some experimenting, it turned out that using 8 x interpolation for the DI 16 (8 x 3 TDA1543), resulted in a closer match with the DI 8M. So now the difference in sound quality is not so big anymore. Even the 8 x 2 configuration (using the same amount of DAC chips / similar THD), already resulted in a better match. So there are indications that 8x interpolation works better with a DI DAC. When using more TDA1543 chips in parallel, performance could be further improved, but after making some calculations, it would be quite problematic to obtain the same low distortion as with the TDA1541A, if possible at all.

The TDA1541A with it's 10 times lower distortion, used in a DI 8 configuration is quite difficult to beat. The calculated DAC chip THD of the DI 8 equals approx. 0.0006%, the DI 16 (8 x 3) equals approx. 0.0036%. THD is only one factor that determines DAC sound quality, but the lower distortion is a fact, and it is audible.

The audio equipment used must also perform at a high level in order to clearly hear all advantages of the DI 8M in full detail.
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Old 1st June 2007, 06:24 AM   #1522
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Default 352.8 KHz DEM clock schematics

Hi all,


I mentioned the new 352.8 KHz DEM clock circuit a number of times now,

Here it is, I attached a diagram of the 352.8 KHz DEM clock I currently use.

Depending on BCK frequency, BCK needs to be divided by a specific factor in order to get 352.8 KHz. When BCK equals 2.8224 MHz, a divide by 8 counter is needed, with other BCK frequencies the division factor needs to be adapted.

2.1168 MHz > divide by 6
2.8224 MHz > divide by 8
4.2336 MHz > divide by 12
5.6448 MHz > divide by 16
11.2896 MHz > divide by 32

Division factors like 6 and 12 can be obtained by resetting the synchronous counter, depending on a specific counter output code. Division factors like 32 can be obtained by cascading synchronous counters. This is achieved by connecting the clock inputs (pin 2) together, and connecting the TC output of the first counter (pin 15) to both CEP (pin 7) and CET (pin 10) of the second one.

When using a synchronous counter with asynchronous reset like the 74HC161, a divide by twelve counter can be constructed by resetting the counter at output code 1100 (12). This will produce an asymetrical output signal. To correct this a divide by 6 counter can be constructed (reset code 0110), followed by a synchronous divide by 2 counter.

When using synchronous counters with synchronous reset like 74HC163, the same divide by 12 counter can be constructed by resetting the counter at output code 1011 (11) as the synchronous reset causes a 1 clock delay.

Resetting is done by using a NAND gate like the 74HC00 (dual input), 74HC10 (triple input) or 74HC20 (quad input) between outputs and the 74HC161 / 74HC163 reset (pin1). The "1" represented in the counter output code should be connected to the NAND gate inputs. So an output code of 1011 (11) would require 3 inputs (74HC10).

Don't use asynchronous ripple counters like the 74HCT4040, these will introduce unwanted delays that in turn cause inter modulations.


If multiple DAC chips are used, a common synchronous divider is used for all chips. Each chip needs a separate attenuator (680R / 180R), timing cap (470pF) connected to pin 16 and decoupling cap (100nF) connected to pin 17, this is also illustrated in the diagram
Attached Images
File Type: jpg demclk.jpg (50.5 KB, 1625 views)
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Old 1st June 2007, 11:10 AM   #1523
oshifis is offline oshifis  Hungary
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Very interesting and useful circuit. I am a bit afraid, though, that there is some uncertainity of switching time (jitter) at the output of the 74HC161. I added a very simple reclocking right at the latch input of the TDA1541A. It is an old 74S74 high-speed D-type flip-flop. The original latch signal goes to its D input, and it is clocked from the master clock. Its Q output follows the D input precisely when the master clock next goes high. It reduces the jitter of the latch signal that might be produced by the previous circuitry. The same principle could be used after the DEM clock divider, utilizing the other half of the dual D-flip-flop. This also synchronizes the DEM clock positive edge with the DAC latch positive edge.
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Old 1st June 2007, 08:59 PM   #1524
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Default Re: 352.8 KHz DEM clock schematics

Quote:
Originally posted by -ecdesigns-
Hi all,


I mentioned the new 352.8 KHz DEM clock circuit a number of times

Quite frankly I tried both the old schematic at the beginning of this tread , and this last one .

Both exibit rather high distorsion at low levels playing music when applyed to the TDA1541A . Distorsion is data corruption alike .
The dac is with the CS8414 . Can it be so jittery to cause all of that , when without the DEM clock circuit it *seems* to work ok ?

Other people experienced that ? what about other DEM circuit reclocking used in combination with a spdif receiver ??

Thaaanks
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Old 1st June 2007, 09:25 PM   #1525
tubee is offline tubee  Netherlands
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Default Re: Re: 352.8 KHz DEM clock schematics

Quote:
Originally posted by stefanobilliani



Quite frankly I tried both the old schematic at the beginning of this tread , and this last one .

Both exibit rather high distorsion at low levels playing music when applyed to the TDA1541A . Distorsion is data corruption alike .
The dac is with the CS8414 . Can it be so jittery to cause all of that , when without the DEM clock circuit it *seems* to work ok ?

Other people experienced that ? what about other DEM circuit reclocking used in combination with a spdif receiver ??

Thaaanks
I have heard artefacts in treble, once in a while. Used simple dem schematic with 161 or 163 divider to 176kHz, and no voltage divider, a coupling cap to pin 16 and pin 17 free floating. Replaced the 470pF cap later. Will try the new dem soon, have parts.

Btw (off topic): changed the 1N4007 diodes in HT PS from my hybrid power amp in BYV27-C's, sound is les coloured, cleaned up a lot. But have to get use to it, sometimes it's some "cold" and more remote. (analytic?)
Will try National HFA08TB60 8 amp. hexfreds in current section (powerfets) soon.
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Old 1st June 2007, 10:06 PM   #1526
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Default Re: Re: 352.8 KHz DEM clock schematics

Quote:
Originally posted by stefanobilliani



Quite frankly I tried both the old schematic at the beginning of this tread , and this last one .

Both exibit rather high distorsion at low levels playing music when applyed to the TDA1541A . Distorsion is data corruption alike .
The dac is with the CS8414 . Can it be so jittery to cause all of that , when without the DEM clock circuit it *seems* to work ok ?

Other people experienced that ? what about other DEM circuit reclocking used in combination with a spdif receiver ??

Thaaanks
Stefano,
where are you taking the "master" clock from? Maybe the BCK from CS8414 to TDA?

How does the waveform on pin 16 look like?

Cheers

Andrea
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Old 2nd June 2007, 07:42 AM   #1527
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Default DEM clock

Hi stefanobilliani,


Quote:
Quite frankly I tried both the old schematic at the beginning of this tread , and this last one .

Both exibit rather high distorsion at low levels playing music when applyed to the TDA1541A . Distorsion is data corruption alike .
The dac is with the CS8414 . Can it be so jittery to cause all of that , when without the DEM clock circuit it *seems* to work ok ?
First of all you need to verify if the DEM clock circuit is functioning correctly. Conclusions are only valid with a correct working DEM clock.

I had similar problems with the first DEM clock I published last year, it didn't have the 100nF decoupling cap on pin 17. The attenuator must also be placed very close to pin 16, 17 and the GND connection, in order to avoid interference signals on the sensitive DEM clock oscillator input pins (pin 16 and 17).

The distortion you describe is that of a non-functional DEM clock (DEM clock is not able to drive the TDA1541A internal shift registers) so they stop, and low level distortion increases significantly as the Dynamic Element Matching system is no longer working. It is not caused by the CS8414.

I checked the DEM clock waveform on pin 16 with an oscilloscope, and removed a decoupling capacitor (MSB) to check the active divider output (20mV range), when the DEM clock functions correctly, a step shaped signal should be visible, it should have equal time for each step. The step pattern is caused by tolerances in the passive current divider (part of the active current divider).

I will try to post photograph showing both, DEM clock signal shape on pin 16, and the step signal on MSB (decoupling capacitor temporarily removed).

When both signals are correct, the DEM clock is working correctly, and low level signals should have very low distortion.
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Old 2nd June 2007, 07:47 AM   #1528
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Hi oshifis,


Thanks for your reply,


Quote:
Very interesting and useful circuit
The external DEM clock circuit resulted in the biggest improvement of TDA1541A performance so far.

I already tested 74H..74 chips, they had the worst jitter specs from all D flip-flops I tested, so I don't use them anymore. Using 2 D flip-flops in the same housing for different frequencies causes crosstalk and should be avoided. Unused INPUTS should always be connected to a steady signal level (GND). I got lowest jitter using D flip-flops from 74HC164 and 74F164 shift registers, that's why I use them a lot for timing critical circuits. The lower jitter is probably caused by the chip internal circuit architecture.

The 74xx161 is a synchronous divider. This means that the outputs change state fully synchronous with the input clock signal (BCK). The 74HC161 triggers on the positive going edge of BCK, this means that 74HC161 outputs also change on the positive going edge of BCK. The jitter at the divider outputs is very low (comparable to 74HC164), reclocking it with a 74..74 would actually increase jitter.
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Old 2nd June 2007, 09:56 AM   #1529
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Default Re: DEM clock

Quote:
Originally posted by Andypairo


Stefano,
where are you taking the "master" clock from? Maybe the BCK from CS8414 to TDA?
Cheers
Andrea
Hello Andrea ,
The BCK is from the TDA1541A pin 2 , closely . Of course it comes from the CS8414 in this case .

Quote:
Originally posted by -ecdesigns-
Hi stefanobilliani,
First of all you need to verify if the DEM clock circuit is functioning correctly. Conclusions are only valid with a correct working DEM clock.

I had similar problems with the first DEM clock I published last year, it didn't have the 100nF decoupling cap on pin 17. The attenuator must also be placed very close to pin 16, 17 and the GND connection, in order to avoid interference signals on the sensitive DEM clock oscillator input pins (pin 16 and 17).

I checked the DEM clock waveform on pin 16 with an oscilloscope, and removed a decoupling capacitor (MSB) to check the active divider output (20mV range), when the DEM clock functions correctly, a step shaped signal should be visible, it should have equal time for each step. The step pattern is caused by tolerances in the passive current divider (part of the active current divider).
Hello ecdesigns ,

Well the circuit is working ok . The cure was to put it very close to the pin 16-17 . Before I had it at 5 cm , while the BCK was connected at 1 cm distance , the output of the DEM reclock was too far . By very close I mean 1 cm or so.
Very nice improvement , now the distorsion at low levels is almost complitely gone . .... need to put the ear close to the speakers ( 96db 1W meter ) to detect some artifact .


Sorry no Scope yet ... but I wish ...
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Old 2nd June 2007, 11:31 AM   #1530
tubee is offline tubee  Netherlands
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My Ecdesigns dem-clone is working too
Sounds good, its getting more to the core of the music, bass is deeper and clearer. Just putted it on, it has to warm up. I divided 11Mhz/16 (from dividerchip to 1541) and then with the suggested HCT161 /2, gives 350kHz.
Will see with scope how waveform looks.
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