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Old 13th February 2010, 07:34 AM   #611
loris.p is offline loris.p  Italy
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Hi John,
I'm looking at the Prague Astronomical Clock on this webcam:
Prague webcam - Live webcams in Prague (including Prague castle webcam)
Are you in Prague? Where?

After 72 hours hooked to the dvd/cd player via optical, no noise.
Now I've switchd to the Cardinal via the clock-lock dic.

How's your dog? Did he grow up? My cat did
Loris
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Old 13th February 2010, 11:17 AM   #612
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Quote:
Originally Posted by JohnW View Post
Hi Aparatusonitus,

Close your getting the idea, but....

Firstly, the XSYS 2 is very heavily jittered by the internal clock tree of the 7350. In your current implantation (if it worked), the final pulse energy would be also modulated by the jitter on the output of XSYS2.

Other issues - I cannot see how it would work... I will forward you a Schematic in the next 24 hours...

John
Thanks John for your support...BTW do you know what is delay between XSYS2 and MCLK 'cos SAA7350 datasheet doesn't clearly point that out?
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Old 13th February 2010, 01:09 PM   #613
JohnW is offline JohnW  Hong Kong
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Hi Aparatusonitus,

Here's the schematic I promised - as you will see, it’s not really suitable for DIY - due to layout requirements, Fine Pitch SMD & "hard to source" in small Qtys. components, but still you can get an idea.

1. The Master clock is based upon a simple Pierce Oscillator – Logic Gate Pierce Oscillators get bad press – however due to high current drive of the crystal element, they are good for short term stability which we care about the most for Audio (Long-term’s a little like a drunken sailor).

2. The Pierce is then buffer by single packaged dual Gate NC7WZ04 (Dual Gates operated in parallel to reduce output impedance and -6dB reduction in close-in Flicker noise etc).

3. U7 / U9 buffer / Isolate the L/R DAC channels paralleled once again for the same reason's as above.

4. U8/U10/U11 Inverter Chain Buffer / Invert the Clock to insure that the critical DAC elements (U2A/B and U4A/B) are operated during “Silent conversion” period – Due to the clock phase inversion, the rest of the unit which is Positive edge triggered is operated out-off-phase to the final DAC section, reducing Ground impulse currents flowing during the critical DAC conversion “Edges”

5. U2A/B & U4A/B (Pls. ignore IC pin numbers these are for the single UHS D-type). Use the Dual Packaged 74VHC74 (TSSOP14) in this Position, Ground / PSU currents will be (almost) “DC’ed” by the Balanced output current flow.

6. U1A/B and U3A/B Pre Latch the Data on the now Phase inverted Clock edge, insure adequate Set-up and hold times for the final DAC elements, and further improve Jitter Attenuation.

7. U12, U13 provide the complimentary Data Q / Q- (latched to XSYS2), note that the Final Latches U1,U2,U3 & U4 are operated from 16.9344MHz to insure discrete “PDM” type data pulses.

8. The Final fully Balanced Ground reference 2nd Order output filter (I grabbed from an earlier design to save time, I recall Fc was around 70KHz) – Fc should be set lower, the NS in the 7350 are only 3rd order, I would move Fc to around 22KHz…..

9. Resistors must have low Voltage coefficients, use 1206 Size Min, 0207 type MELF are the best. The Capacitors in the LPF section should be Polypropylene film type, never EVER use ceramic SMD types – leave these for PSU Bypassing / decoupling.

10. The whole clock section should have its own Low Noise PSU rail (U5, U6, U7, U8, U9, U10, U11), as should U2A/B (DAC Left), U4A/B (DAC Right), U12, U1 (5V Left) & U13, U3 (5V Right). These 5 sperate PSU Rails must be Ultra Low Noise types. The LM317 type Regs. can have nasty loop response (read Peaks) within the Audio Band (Peaking typically around 1-2KHz).

11. It’s VERY important to pay special attention to PSU decoupling of EACH of the CMOS logic IC’s which are used here in an “Analogue” Mode, think of the Loop area of the decoupling Caps. (Loop between Vdd and return Ground pin around each IC).

Good luck – then you will have your own Dacapo DAC
Attached Files
File Type: pdf 1Bit RTZ DAC Section.pdf (27.2 KB, 106 views)
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Old 13th February 2010, 01:44 PM   #614
JohnW is offline JohnW  Hong Kong
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Hi Loris,

While we are in Czech Rep. we are located about 70Km east from Bruno, just outside Olomouc, up in the hills - where snow ploughs dare not venture.... We normally use our Range Rover during this time of year - but being of good heart and stupidly I lent it to my good friend while his own Range Rover sport is being repair (air suspension let him down) - leaving use to slide somewhat less-then “gracefully” around in our new but now with shortened boot car...

Bobby (our Dog), was “fully” grown in the picture I last posted next to your Dacapo PCB, although he has gotten just a “Little” fatter…

The Dacapo only works correctly with 44.1 KHz source – so pay attention when using your DVD player – Most DVD players output 48 KHz while playing DVD’s

John
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Old 13th February 2010, 02:06 PM   #615
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What can I say...you are unique, thank you very much from bottom of my hart John! If you ever come to Croatia and my home town Split, you will be treated like king.

I'll try my best to develop pcb artwork for this beauty, but as I'm an analog guy, I'll will need some help from time to time.

As for U2/U4 1-bit dac and subsequent analog LP filter stage, in order to avoid opamps, how do you feel about passive proposition below?
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Old 13th February 2010, 04:28 PM   #616
JohnW is offline JohnW  Hong Kong
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Hi Aparutusonitus,

Sorry I made an error in the PLM to PDM decoding section (I worked with the SAA7350 17 years ago now), pls. see the corrected schematic (Note the addition of the “AND” Gates). The 2 series connected AND Gates are to compensate for the propagation delay of the D-Latch, without you would get short "runt" pulses – Sorry somewhat crude but works...

The output from the DAC section should not be considered “Balanced” as in the conventional sense of the term. The DAC section has two outputs, but they need to be correctly summed to fully reconstruct the Modulators intended output. Only once both outputs have been correctly summed will you have the correct output. This is the function of the differential OPAMP’s.

In fact, only the crossed coupled differential OPAMP’s generate the correct “Balanced output”.

1. The Common Mode component (2.5V) is rejected.

2. With this crossed coupled arrangement both “arms” of the DAC element see the SAME load impendence – this is very VERY important for the reconstruction of the correct pulse energy levels - the Latch outputs do not have zero output impedance - the error source here being the differences in the Latch's High and Low output impedance. If they both H & L state where identical, there would be no issues, irrespective if Zero Ohms or not. However Latch output impedance should also be taken into consideration when design the LPF.

3. The finite difference in edge Rise and Fall times (read the differences in energy contribution from the pulse edges) is fully compensated.

4. Both + and - going pulses from the Bitstream Modulator are correctly summed - these are not symmetrical (the Data is not the same).

There’s much more going on then at first meets the eye – while it might appear simple, it’s like peeling an onion... many layers of complexity…

I understand you comments on OPAMP’s – however I suggest using OPAMP’s with FET inputs, biasing into Class A, and adding a Diamond buffer on the output – then they are not too bad… In the above circuit configuration, they are being used in RF filtered “Voltage Mode” not as I to V converters without RF filtering – makes a huge difference.

John
Attached Files
File Type: pdf 1Bit RTZ DAC Section Rev2.pdf (29.1 KB, 95 views)
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Last edited by JohnW; 13th February 2010 at 04:46 PM.
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Old 13th February 2010, 05:38 PM   #617
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Thank for the update John, obviously you have a sweet spot for SAA7350 dac, just like me

I have a few questions (at the moment ;-) for you:

- what will SAA7350 do if fed by I2S (1 x Fs, 44.1kHz) directly...will it do zero-order hold or inverse decimation (or something in between) with input data at 1 x Fs...will it have typical dB or two loss at 20kHz like multibit non OS dac? Datasheet is not clear about that...I know it will work, and work very good if I may say, already tried that bypassing dig. filter in one of my cd players.

- what is delay between MCK and XSYS2?
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Old 14th February 2010, 04:15 PM   #618
loris.p is offline loris.p  Italy
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Default DaCapo

after almost 3 days of continuous working......
the noise is back
The noise comes only from locked inputs, it's the same from optical dic or clock-lock dic, the noise is higher if some music is playing.
I changed the filter but it's the same thing.
Loris
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Old 15th February 2010, 05:46 PM   #619
JohnW is offline JohnW  Hong Kong
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Sorry to hear about this, however I'm not surprised as I expected that replacing the capacitors would not solved the root issue.

When the Dacapo is not locked the audio output is muted - so you would not hear the white noise.

It sounds like a Clocking issue on your unit, but without having the unit or my Lab here in Europe, it’s hard for me to resolve.

I know you don’t want to hear this, but Dacapo's are getting old now - I understand your "love" of there sound - But I do strongly recommend trying a Peachtree Audio iDecco. The DAC section shares many off the audio virtues of the Dacapo - I'm sure it well not disappoint. If you want something cheaper then the AudioLab MDAC or 8200CD once they hit the shops.

OK a promise, once I get back to China, as I cannot repair the failed clock section under the potting compound, I will "fix” your first Dacapo PCB to work with external clock locked Cardinal transport – so you have a “Working” Dacapo – but really, have a listen to the above units..

Just found the 6moons “pre-review” of the iDecco, with many close-up internal pictures…. I have no idea what the reviewer will say, Dominik and I have little contact with Peachtree Marketing, we only design the products and arrange the China manufacturing, insure QC and prevent “Quality Fade”…

6moons audio reviews: Peachtree Audio iDecco

John
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Old 15th February 2010, 06:02 PM   #620
JohnW is offline JohnW  Hong Kong
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Hi Aparutusonitus,

I have no idea what the 7350 would do at 1Fs input, as you say it works, I suspect it just resample the same input date 4 or 8 times... Not something I would want to try.

MCLK / XSYS2 Delay, once again no idea, but I can measure for you once I return to China, its not Specified, but I expect it to be fixed within reason (it should not drifted - or vary much between silicon). I seem to recall it could reverse phase sometimes in relation to MCLK - and in this Mode, the Dacapo would have a slightly different measured performance.

John
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