Hi QUANTRAN,
Sorry for my late response but I feel unease to just exploit your ideas and long time experience. Otherwise the best and cheapest solution for me would be to ask for the schematic which is not fair enough. Anyway I dream for a DAC based on pcm63 with direct I/V conversion buffered by double triode /BENDIX 6385/.
Best regards,
Ignat
Sorry, my hard drive that contained this design died many years ago. I remember that I was using cs8414 in a special mode where sck should be fed by external clock signal. 74hc74 is just for dividing the clock.
Dear Quantran,
Thank you very much ,for your advise .I have read cs8414 datasheet and compare your schematic that you post as attached.May I ask you more.Can I run CS8414 with I2S mode and use FS out from pin6 of the 3rd 74HC164 by use SCK output from CS8414 for PCM63?
Attachments
I think you can with some modifications. In I2S mode, timing of sck and data relative to fsync is different from the mode that I use. The modifications may involve shifting fsync by one more sck cycle and you need to check whethe sck rising edge is the same or not. In some mode data bit is output on rising edge of sck while in other mode data output at falling edge.
Dear Quantran,
Thank you very much for your advise . I already do as your schematic but connect fsync output from pin11 (Q5) of the 3rd 74HC164 and the circuit is work.
Excellent. Pin 11 is right because data line in i2s standard is delayed 1 sck after fsync.
If your sck has low jitter then the result will be very good because sck controls the timing of latch enable signal.
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