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Old 29th January 2005, 01:47 PM   #1
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Default clock division for LRclock and bitclock

I've searched and searched, but cannot come up with many relevant posts.

Using an ad1896 in slave mode for 192khz operation. One needs to derive LRclock and bitclock from the local masterclock.

I've used a pair of 74AC161 dividers, and also tried a 74HC4040. I gather these are not the low jitter solutions I'm looking for.

I can easily see how using a 74lvc1g79 or similar picogate d type flip flop to obtain our divide by 2, but I need help/a shove in the right direction to obtain 192khz from the 24.576mhz.

Thanks for any help,

Mark
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Old 29th January 2005, 02:46 PM   #2
Bricolo is offline Bricolo  France
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divide by 128, 2^7
so, a 8 bit counter or FF in series

but I'm not sure that many FF will result in less jitter than one IC counter
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Old 29th January 2005, 03:38 PM   #3
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With Fs at 192K, BCLK at 64Fs and MCLK at 24.576MHz, two 74HC163 will suffice. BCLK is MCLK/2 and Fs is MCLK/128. The first 163 will have outputs of /2, /4, /8 and /16 and the second /32, /64, /128 and /256.
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Old 30th January 2005, 03:58 AM   #4
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has anyone tried any of the onsemi clock dividers?

http://www.onsemi.com/site/products/...00.html?id=203


Possible 2 of the MC10EP139? (there are 7 pages of division chips there!)I can just solder the qfn package
3ghz max clock speed. random jitter rms of <2ps

failing an on semi clock divider, a 74lvc163 is looking good

Mark
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Old 6th October 2008, 12:35 AM   #5
tallica is offline tallica  Poland
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Hello, could someone look at this schematic? I hope it's ok.
Attached Files
File Type: pdf ad1896.pdf (10.8 KB, 44 views)
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Old 6th October 2008, 07:14 PM   #6
gmarsh is offline gmarsh  Canada
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Use both halves of a 74xx393 gate. This will give you 64Fs or 32Fs (for 32 bit and 16 bit audio output) and 1Fs.

If you're worried about jitter on these lines, you can retime these outputs using a 74xx74.
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Old 6th October 2008, 07:19 PM   #7
gmarsh is offline gmarsh  Canada
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Also, I'd give the AD1896 its own MCLK clock - 25MHz or 27MHz.

Reason being the '1896 will only accept a sample rate as high as 128*MCLK. If your onboard oscillator is dead accurate at 24.576MHz, and someone plugs in a 192KHz signal source that's just a few ppm higher, the AD1896 won't lock onto it.

25MHz lets you handle a 195KHz input sample rate, which is well outside what any "ordinary" 192KHz source could provide. 27MHz allows a 210KHz input.
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Old 6th October 2008, 07:58 PM   #8
tallica is offline tallica  Poland
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Thanks for reply. Datasheet says: "The master clock has to be at least 138 times greater han the maximum input or output sample rate." So I will need two clocks ~27MHz for MCLK and 24,567MHz for BCLK/LRCLK. Isn't it a problem? I mean... putting two oscillators for one chip? I was thinking about using PLL1708.
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Old 6th October 2008, 10:45 PM   #9
tallica is offline tallica  Poland
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OK, I've recreated schematic. What kind of chips should I use? 74VHC393/74VHC74?
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File Type: pdf ad1896.pdf (10.7 KB, 33 views)
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Old 7th October 2008, 02:58 AM   #10
gmarsh is offline gmarsh  Canada
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The /16 output of one half of the '393 has to feed the CLK input of the second half of the '393.

VHC is a good logic family, and the AHC family from TI is good also.
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