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Old 30th April 2004, 08:16 PM   #1
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Join Date: Apr 2004
Location: Bukit Timah, Singapore
Default TDA1545 Reclocking Problem

Hi

I recently built a zero sampling DAC using the CS8412 and TDA1545a combination. CS8412 is giving output in mode 5.
I also built a Async Reclocking based on DDDAC's design, an XO at 11.2896MHz and divided by a binary divisor to give the correct Fs.

I wanted to put it into the DAC but couldn't find the " in" mode for Mode 5 LSBJ format on the datasheet. The DDDAC uses I2S format, so there is both "in" and "out" mode available.

Any advice would much appreciated.

thank you.
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Old 1st May 2004, 04:41 PM   #2
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Join Date: Apr 2004
Location: Bukit Timah, Singapore
Hi all,

Maybe allow me to rephrase my question:
Is it possible to configure the CS8412 in mode 5 -16bit LSBJ to accept SCK and FS as an input signal.

For the I2S format, the choice is between mode 2 and mode 3.

Any advice on an alternative approach to reclock these signals is much appreciated.

thanks in advance for your assistance.
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