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Old 27th April 2004, 01:28 PM   #11
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Quote:
Originally posted by Bricolo
But where's the cascode here

I don't see a cascode in your circuit, nor in Pass Labs original D1 one (the second transistor is a buffer, not a cascode)

Bricolo,
the DAC is looking for a virtual ground - the source of the mosfet .Than the signal is amplified in voltage by the mosfet that is in common gate mode .
If not cascode , than what?
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Old 27th April 2004, 01:37 PM   #12
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Quote:
Originally posted by stefanobilliani



By "leave out the vref resistor" I meant just to let the pin 7 of 1543 disconnected.

For the TDA1543 not 0volts but 2,0 or higher voltage .

I also will try soon the circuit with the 1545A.
Hello Stefano,
I hadn't noticed that...this way you switch off the internal current sources of the 1543 and feed its outputs (that now act only as current sinks if I understand right) through the Mosfet, which seems to be configured as a common gate.... the 3k3 sinks further 10mA to keep the fet well polarized and the current variations due to the DAC are reflected on the 680R resistor... very clever!
Did I get it right?

Cheers

Andrea

PS For the balanced are you still using the circuit posted some time ago?
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Old 27th April 2004, 01:51 PM   #13
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Quote:
Originally posted by Andypairo

Did I get it right?
Your description is good thanks.

Quote:
Originally posted by Andypairo
For the balanced are you still using the circuit posted some time ago?
NO.

I think I'll post tonight the arrangement, based on XOR gates that acts as buffers and inverters.
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Old 27th April 2004, 02:13 PM   #14
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I'm looking forward to see it!

Cheers

Andrea
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Old 27th April 2004, 03:10 PM   #15
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YESSSS!

Thats was the piece of the puzzle that I need to figure out. That helped a lot. I did know that this chip has dc output voltage- well I have dac at home- but don't ask me why I didn't figure it out. Maybe I'm to stupid or something - maybe it was blocked for me to get to know today. I don't know- anyway it was a great help.

I REALLY WOULD LIKE TO SEE THAT ARANGEMENT OF YOURS Mr. Bilianni. I have thought to make it ballanced this time but with a single TDA chip (not in paralel). My friend has aleph 5 and aleph 1.7 is on the way and this arangement would be so helpfull I can't tell You how much. It would save me some time of thinking and making questions on the forum.......
regards
daniel
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Old 27th April 2004, 07:21 PM   #16
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Default Balnced Arrangement

OK this is the actual balanced DAC arrangement .Of course it is simplified a lot in the sense that some care has to be taken for the shielded connections , the decoupling caps, ferrite beads and low noise power supplies.

Some thing can be of help BTW:

The buffers need its own PS or at list they can be attached at the DAC VCC but for the SN74HC86N the limit is 7V AND NOT 9V like the 1543.

The 1543 needs its own PS.

The buffers can be mounted close to the dacs , maybe it would be better maybe not.

The Tent clock needs its own PS of course.

The Passlabs D1 stages needs its own PS : +/- 30volts.

The I2S and cloock lines outside the player MUST be shielded .

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Old 27th April 2004, 07:27 PM   #17
Bricolo is offline Bricolo  France
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Does anybody have an idea of the influence of glue logic on jitter on the I2S lines?
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Old 27th April 2004, 09:17 PM   #18
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Thanks mr. Bilianni!
It is very similar like in the D1 d/a converter (in fact the connection is the same). One more thing- because I have allways wondered about that- You connect everything together like in those schemtaics (that is not a problem to me) and how do You set this thing to work properly? I know that I should have 2 volts on input of the i/v and I know that it should be trimmed with VR1 but from which side do You start- from which value of the VR1. Please understand, I don't want to destroy my TDA chip and really I don't know very much about them so I must ask.
I don't know if my dac would live long enough for his i/v to get trimmed.
I would appreciate if nobody would laugh at me and if somebody would help me to understand.
Regards
daniel
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Old 27th April 2004, 09:25 PM   #19
guido is offline guido  Netherlands
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Default Re: Balnced Arrangement

Quote:
Originally posted by stefanobilliani
OK this is the actual balanced DAC arrangement .Of course it is simplified a lot in the sense that some care has to be taken for the shielded connections , the decoupling caps, ferrite beads and low noise power supplies.

Some thing can be of help BTW:

The buffers need its own PS or at list they can be attached at the DAC VCC but for the SN74HC86N the limit is 7V AND NOT 9V like the 1543.

The 1543 needs its own PS.

The buffers can be mounted close to the dacs , maybe it would be better maybe not.

The Tent clock needs its own PS of course.

The Passlabs D1 stages needs its own PS : +/- 30volts.

The I2S and cloock lines outside the player MUST be shielded .

Two idea's for improvements:

reclock all the data with FF's: use '74 so you don't need inverters and reclock with the tentclock. You will loose jitter created by the 7310 (don't know the timingrelation between 7310 I2S out and it's clock input but it should be possible). Maybe you need to invert the clock to the 7310.

Second, obvious (coming from me ): split left and right into two
I2S streams and use one dac for left and one for right.

Greetings,
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GuidoB
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Old 28th April 2004, 12:01 AM   #20
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Default Re: Re: Re: The Pass D1 For Tda1543

Quote:
Originally posted by stefanobilliani



I quote MR Pass from a Passlabs thread:




...

You are confusing the specific with the general.
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