General DAC design rules, layout techniques, etc.

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
I have decided to open this topic because of some not fully understood (at least for me) phenomenon in term of DAC designing, (HF) layout rules and so on...

Primarily without specified IC manufacturers, but of course by practical examples we must mention this things for a better understanding.

It can be referred to or quoted from literature (books, manufacturer app. notes), and/or posting some own or foreign designs (please be aware of copyrights) to presenting detail solutions.


Some points for example:

- applying copper pour and determine clearance by HF signals (e.g. I2S lines) to avoid unwanted stray capacitance that degrades signal quality

- proper determining of I2S resistors at the DAC input pins (to prevent overshooting in the signal edges)

- importance of Vref (reference voltage), what type of current they exactly need (datasheets do not give too much informations about that e.g. by AK44xx DACs)

- ground connenction of bypass caps (bigger electorites and small ceramics): simply to common ground pour or preferred a star grounding terminology?

- ...


:confused: -> :magnify: -> :)
 
Having done a few DAC layouts myself this looks a little bit ambitious because you're keeping it so generic. My suggestion would be to work from a specific example layout with a particular DAC chip towards general principles. The simpler the DAC chip the better, to begin with.
 
Ok, let's start...:)

My actual project (my 2nd DAC) is a multichannel AK4458, for an active speaker. The concept is 2 boards with 10x10cm, one for the DAC and the other for the output filter OPSs, under them.

If I fill the PCB with copper pour, what is the desirable clearance value? The manufacturer can produce down to 6mil I think. My actual setup is 15mil. I ask this because I’ve read the slyp173 document from TI (www.ti.com/lit/ml/slyp173/slyp173.pdf) that writes that we must take care about stray capacitance by HF signals (it can degrade the signal shape). This means for us that at the digital I2S lines, especially at the system clock (>1Mhz) we should avoid the pouring around this lines? On the bottom side I would keep the ground plane anyway because of reducing the current loops (impedance).
 

Attachments

  • DAC_1.JPG
    DAC_1.JPG
    141.4 KB · Views: 646
I2S resistors at the DAC input:

How can I determine the optimum value? These resistors are for reducing the overshooting of the HF signals rising edge. Should I experiment with different values and check with oscilloscope? Or simply use e.g. 50 Ohms? I have originally placed on the PCB patterns for SMD and through-hole resistors too for easier changing by experimenting with them. But I’m considering to leave them because of the pads on the bottom layer, they make shortage on the ground pour for HF returning currents.

(The boards have only 2 layers. For my 2nd project it will be enough...)
 
Last edited:
Your talking about source series termination, usually you chose the R to be the same as the transmission line Z, but in practice you can use a scope to fine tune the R to reduce/damp the ringing.
Another technique is to use some thevenin terminations, they can limit the V swing,slew and thus reduce emissions.
I find changing smt R's a lot easier/faster than a TH R, I use two irons with small tips, and heat both pads at the same time, takes seconds.
 
Thanks rsavas!
I've decided to delete the through-hole axial resistor pads and keep only the smds.

I'd like to have the option of U.FL coax connector in that case I apply an external clock. (Currently I will drive the DAC with miniDSP USBstreamer, it can operate only in master mode). But if I place this terminal, should I after (like in the picture) or before the termination resistors??
 
Some points for example:

- applying copper pour and determine clearance by HF signals (e.g. I2S lines) to avoid unwanted stray capacitance that degrades signal quality

- proper determining of I2S resistors at the DAC input pins (to prevent overshooting in the signal edges)

I usually start with checking the characteristic impedance of the line and the ground plane below it, using online transmission line calculators or the calculator in KiCAD. I then check how much clearance to copper pour on the same layer is needed to keep it from changing the characteristic impedance significantly. Resistors at outputs can simply get a value equal to the impedance of the line minus the (estimated typical) output impedance of whatever is driving the line. I have no idea about resistors at DAC inputs.

- importance of Vref (reference voltage), what type of current they exactly need (datasheets do not give too much informations about that e.g. by AK44xx DACs)

It's extremely important to have a clean reference, because variations of the reference amplitude-modulate your signal, thereby producing undesired sidebands. With noise shaping, high-frequency rubbish on the reference can frequency-convert out-of-band noise into the audio band. I can't help you with poor datasheets, unfortunately.

- ground connection of bypass caps (bigger electrolytes and small ceramics): simply to common ground pour or preferred a star grounding terminology?

There are more strategies that work, but if you can keep the loop area small, it is usually a good idea to connect them to the supply (or reference) pin and ground pin you want to decouple and then straight to the ground plane at one point. That is, you make a small local loop that connects to the plane at one point.
 
Thanks MarcelvdG!
I didn't know KiCAD, but I will see this calculator tool... (I use DipTrace). Thanks for the tip!

I know that reference voltage is extreme important. I'll use low-noise shunt regs near to the DAC chip to supply them, possibly will try LT3042 too sometime...

The reason why I asked this question is that I have the small bypass caps on the bottom layer, and then connected the Vref line through vias to the DAC pins (see picture). This is of course not the best solution, because of vias have some inductance which could decreace the effect of the bypass caps -> IF the Vref pins need HF currents! And this is the point what I do not know, where the HF currents are flowing into the DAC. At the Vref pins or at the AVDD pin (by AK4458 for example)??
 

Attachments

  • DAC_2.JPG
    DAC_2.JPG
    88.2 KB · Views: 579
  • DAC_3.JPG
    DAC_3.JPG
    77.8 KB · Views: 574
Series termination close to the receiver does not usually buy you much, you want the series termination to be close to the transmitter!

If you are going to split the ground plane, you need to make sure that nothing crosses the split on the top side of the board, difficult to tell without a view showing both layers.

You have the analog pairs on your analog out headers, but where are the high frequency grounds? The stuff coming straight out of the chip will likely have significant common mode RF on it (Which is never documented for some reason), and you want to be able to shunt that to ground, before it hits a slew rate limited opamp. I would be building the first pole on the board rather externally to make this more doable.
I really wish the DAC vendors would give an output spectrum extending well into the HF bands and not use a 20-20k filtered number. I should do some work with my SA and see what really comes out of these things up above the audio band.

DACs are to a first order approximation, mixers (in the RF sense of multiplier) and should be treated as such.


Regards, Dan.
 
Ok, calculated without guarding on the top side. And what now...?

Now you can compare it to the "koplanarer Wellenleiter mit Masseflaeche" to get an idea about how far your top layer ground fill must stay from the trace if you want the bottom to be the main return path. Above a certain ground fill spacing the characteristic impedance will stay nearly constant because almost all trace capacitance is to the bottom ground plane and not to the top layer ground fill.

With 125 ohm characteristic impedance, guesstimating 25 ohm source resistance and neglecting the input capacitance of the DAC inputs compared to the traces, you would need a 100 ohm series termination resistor at the source. As the input capacitance of the DAC is not zero, you could round that down a bit to 82 ohm or so.
 
Thanks MarcelvdG!
I didn't know KiCAD, but I will see this calculator tool... (I use DipTrace). Thanks for the tip!

I know that reference voltage is extreme important. I'll use low-noise shunt regs near to the DAC chip to supply them, possibly will try LT3042 too sometime...

The reason why I asked this question is that I have the small bypass caps on the bottom layer, and then connected the Vref line through vias to the DAC pins (see picture). This is of course not the best solution, because of vias have some inductance which could decreace the effect of the bypass caps -> IF the Vref pins need HF currents! And this is the point what I do not know, where the HF currents are flowing into the DAC. At the Vref pins or at the AVDD pin (by AK4458 for example)??

Whether there are significant HF currents flowing through the Vref pins depends on the internal circuitry; do they directly feed the actual DACs or only buffers that feed the DACs? The impression I get from the datasheet, but that's only an educated guess, is that the AK4458 probably contains switched capacitor DACs that are directly charged from the external bypass capacitors, resulting in large current spikes. Having too much trace and via inductance then messes up the settling of the voltage across the DAC capacitors, which could seriously affect the noise floor and the distortion. So I'd do whatever keeps the inductance in the VREFH-decoupling-VREFL loops as low as possible. Vias are inductive, but so are traces. Is there any way you can put the caps right next to each VREFH/VREFL pair on the same layer as the IC?
 
Yep, rule of thumb with delta sigma parts is to assume they are charge transfer devices until proved wrong, and treat them as RF components not audio ones (obviously they are both, but the RF side is usually trickier about layout then the bit down in the wobbly DC region). 0402 and 0603 C0G are very much your friends.

The real gotcha is in ADCs actually, especially fast ADCs where source termination really needs to give good return loss up into the low microwave bands for maximum SFDR.

Regards, Dan.
 
Vias are inductive, but so are traces. Is there any way you can put the caps right next to each VREFH/VREFL pair on the same layer as the IC?

It is not so easy, because of the analog signal pin headers. I'd like to place the voltage regulator circuits as near to the DAC as possible. This means that I have not a lot of space for 2x8=16 audio traces to run across the regulators (don't forget I have only 2 layers), so I've decided to lead them to the filter PCB direct from the DAC pins (see pics before). In that case there are only very small "islands" between them (on the top layer). Probably I can try with 0603 or smaller caps, but I did not find a good solution so far...

It would be advantageuos to know the inseide operation of the DAC but this is unfortunately not the case...
 
Last edited:
If you are going to split the ground plane, you need to make sure that nothing crosses the split on the top side of the board, difficult to tell without a view showing both layers.

You have the analog pairs on your analog out headers, but where are the high frequency grounds? The stuff coming straight out of the chip will likely have significant common mode RF on it (Which is never documented for some reason), and you want to be able to shunt that to ground, before it hits a slew rate limited opamp. I would be building the first pole on the board rather externally to make this more doable.

Splitting the digital and analog ground layers is a recommendation from the manufacturer. There are no crosses, but I can upload my design files if you wish...:)

It is a good question. You mean that the HF components of the analog signal (that must be actually filtered out) want go back to DAC ground? If it is so, the loop must be really small to assure effectivity... But the question is the same: how can I make it with 2 layers and separate filter PCB in all 8 channels? I think I must make serious compromisses somewhere...
 
Yep, my default for more or less anything these days is to start at 4 layers and if I need to go to 6 it does not take that much thought.

Multilayer boards do not have the cost for prototypes that they once did, and being able to bury power and (especially) a real ground plane is all to the good.

I would pick a much denser connector then that .1 inch thing, if you go to a 1 or even 0.5mm pitch board stacking connector from Molex or the like you can shoe horn a lot of ground onto it as well as the audio.

Regards, Dan.
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.