@Markw4 that's a sweet project. I'm a software engineer but I haven't had the time to take on FPGA's yet for FIR but it's been something on my mind. I'd love to see you branch this off into a new thread so it doesn't get buried here. It'll also likely bring some fresh visitors who might be drawn to a more direct thread title about FPGAs.
Looking forward to reading you!
Don't mind Fourrier's transformations, Diracs, Cauchy-Schwarz theorems and why not pushing to fictive powers - although dusty in all these topics since decades - but really not familiar with software or computers. They are FOR ME just a mean and shoudl come ready to (they never are).
BUT interested in the filter's charactaristics, the math / logic behind your developments - might be able to follow you on a potential AKM project, but only if all the software comes ready (thanks to you or else) - no time or sympathy for this part. Again, I admire you get your shirt wet on both theory and implementation, as often required to get special realisations. Bravo again!
Claude
Don't mind Fourrier's transformations, Diracs, Cauchy-Schwarz theorems and why not pushing to fictive powers - although dusty in all these topics since decades - but really not familiar with software or computers. They are FOR ME just a mean and shoudl come ready to (they never are).
BUT interested in the filter's charactaristics, the math / logic behind your developments - might be able to follow you on a potential AKM project, but only if all the software comes ready (thanks to you or else) - no time or sympathy for this part. Again, I admire you get your shirt wet on both theory and implementation, as often required to get special realisations. Bravo again!
Claude
sorry, more noob questions.
So these sabre dacs use an async clock, ignoring I2S MCLK. For the DIYinHK XMOS interface which uses a pair of NDK NZ2520SD (45.158Mhz and 49.152Mhz) to generate MCLK, it is almost definitely a better clock source than whatever the 100MHz clock is in the topping DAC. The original internal XMOS interface in the DAC which broke also has 45.158Mhz and 49.152Mhz clocks
so what exactly is point of the async clock?
From an simplified perspective having the source and DAC synchronised to 1 clock rather than 2 seperate identical clocks seems like it would be better,
and having 2 seperate source clocks for 44.1KHz and 48KHz rates seems better.
The frequency is very high at 100MHz too, the XMOS interface can handle up to DSD512/705.6kHz with 45.158MHZ clock .
Dont higher frequency clocks have more jitter?
Could be totally wrong but I get the impression its for improved versitilty rather than peak performance,
like the DAC could actually perform better in its stock form if it was synced to the USB clocks but then quality of SPDIF input would be suffer, from commercial perpesctive having decent performance on all inputs would be most important.
Anyway, I had some 45.158Mhz and 49.152Mhz clocks that I tried connecting instead of 100MHz clock, with 45.158 the DAC gave a familar error on the display but with 49.152 it did work.
When comparing I expected 48Khz multiple files to sound better with this and they did.
quite frustrating that the 45.158 clock didnt work, because it would easy to connect MCLK from XMOS interface if it did and have much better clocks.
So these sabre dacs use an async clock, ignoring I2S MCLK. For the DIYinHK XMOS interface which uses a pair of NDK NZ2520SD (45.158Mhz and 49.152Mhz) to generate MCLK, it is almost definitely a better clock source than whatever the 100MHz clock is in the topping DAC. The original internal XMOS interface in the DAC which broke also has 45.158Mhz and 49.152Mhz clocks
so what exactly is point of the async clock?
From an simplified perspective having the source and DAC synchronised to 1 clock rather than 2 seperate identical clocks seems like it would be better,
and having 2 seperate source clocks for 44.1KHz and 48KHz rates seems better.
The frequency is very high at 100MHz too, the XMOS interface can handle up to DSD512/705.6kHz with 45.158MHZ clock .
Dont higher frequency clocks have more jitter?
Could be totally wrong but I get the impression its for improved versitilty rather than peak performance,
like the DAC could actually perform better in its stock form if it was synced to the USB clocks but then quality of SPDIF input would be suffer, from commercial perpesctive having decent performance on all inputs would be most important.
Anyway, I had some 45.158Mhz and 49.152Mhz clocks that I tried connecting instead of 100MHz clock, with 45.158 the DAC gave a familar error on the display but with 49.152 it did work.
When comparing I expected 48Khz multiple files to sound better with this and they did.
quite frustrating that the 45.158 clock didnt work, because it would easy to connect MCLK from XMOS interface if it did and have much better clocks.
@laserscape
Allo Katana uses the 'A' Suffix version of the NDK clocks you mention, when is the newer ultra low jitter version. I have a Katana here and although it is pretty darn good with good power supplies, I can match or beat its sound at will with my 100Mhz clock. Sabre dacs can also be run synchronously as you describe, which is exactly what Katana does. According to ASR, Katana measures lower jitter than Benchmark DAC-3. Obviously, there is much more to the story, but you have some catching up to do.
Regarding the point re async clocking, the ESS explanation can be found on their downloads page, but here is the document: http://www.esstech.com/files/4614/4095/4305/about-jitter.pdf
Benchmark DAC-3 and my modded dac have some differences and similarities, but both run async. I may or may not do that if I do another dac. If I do another, I will probably use yet another clocking design which hopefully would be even better than what I have now. It would use one master clock for the bulk of the dac system, but separate clocks for the XMOS board (stock XMOS clocks are fine).
Regarding your experiment with clocks, you are basically right that it is possible to make lower jitter clocks if they run at lower frequencies. But there are ways to reduce jitter maybe even lower. Depends, of course. There are clock multiplier and divider chips that can generate as little as 30fs additive jitter. That means it should be possible to use a much lower frequency clock than ones you are using and end up with lower jitter than you have so far. I suspect that's what Iancanada does with at least one of his FIFO jitter reducers.
Regarding your 45MHz clock, if you have a scope and can use an Arduino I'm sure you could probably troubleshoot. It should work and others have done it.
Allo Katana uses the 'A' Suffix version of the NDK clocks you mention, when is the newer ultra low jitter version. I have a Katana here and although it is pretty darn good with good power supplies, I can match or beat its sound at will with my 100Mhz clock. Sabre dacs can also be run synchronously as you describe, which is exactly what Katana does. According to ASR, Katana measures lower jitter than Benchmark DAC-3. Obviously, there is much more to the story, but you have some catching up to do.
Regarding the point re async clocking, the ESS explanation can be found on their downloads page, but here is the document: http://www.esstech.com/files/4614/4095/4305/about-jitter.pdf
Benchmark DAC-3 and my modded dac have some differences and similarities, but both run async. I may or may not do that if I do another dac. If I do another, I will probably use yet another clocking design which hopefully would be even better than what I have now. It would use one master clock for the bulk of the dac system, but separate clocks for the XMOS board (stock XMOS clocks are fine).
Regarding your experiment with clocks, you are basically right that it is possible to make lower jitter clocks if they run at lower frequencies. But there are ways to reduce jitter maybe even lower. Depends, of course. There are clock multiplier and divider chips that can generate as little as 30fs additive jitter. That means it should be possible to use a much lower frequency clock than ones you are using and end up with lower jitter than you have so far. I suspect that's what Iancanada does with at least one of his FIFO jitter reducers.
Regarding your 45MHz clock, if you have a scope and can use an Arduino I'm sure you could probably troubleshoot. It should work and others have done it.
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Good day! Please tell me if it makes sense to buy this watch to update 404 Not Found 5792M-100M-80M / 32815701795.html? Spm = a2g0s.9042311.0.0.6fac33edRHNN6R. Or is it a waste of money?
This Быстрая Бесплатная доставка Позолоченные TCXO 0.1ppm 12 м 13 м 24,576 м 22,5792 м 100 м 80 м 16,9344 М 24 м Пользовательские точки частоты tcxo купить на AliExpress
Or is it worth 49.152 MHz to improve jitter? And the watch is crystek? Or 100 MHz? ))
Or is it worth 49.152 MHz to improve jitter? And the watch is crystek? Or 100 MHz? ))
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888777, The clock you linked to may be a little better than the other Chinese clocks, or maybe not. They sell for about $10 on ebay in the US. A Crystek 575-100-50 or 575-100-25 costs about $25 - $28 here and is no doubt much better. For most Sabre dacs, unless you do a lot of work to fix all the problems, a clock can only help so much. However a real Crystek 575 on its own dedicated 3.3v regulator is a worthwhile upgrade. I would recommend fixing any voltage output stage into a 3-opamp output stage, and fix the AVCC supply too first. Those things will probably help more at first. But, the clock should probably come next. Or, if you plan to do all three mods, then the clock could be done first. Or, you could just do the clock. However, only using a 49MHz clock without programming the dac registers to take best advantage of it, is not something I would probably do.
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I cant really see an advantage to async if the source and DAC are using 2 of the same spec clocks, unless its that you are isolating the DAC clock from interference from the source. It'll be best just to test it out, that will also confirm if the error with 45M clock was caused by that clock or the DAC.
Unrelated but adding the Rasmussen filter to this DAC helped hugely, just as advertised the effects were not subtle.
all that was added was 0.1uf in parallel, no resistors, still have to try different values.
I seen that you did something similar with twisted wires close to the ground plane, maybe thats all it takes but id definitely try it out and see.
Someone mentioned you need use SMD caps because inductance of the legs of through hole cap will cancel the effect, I used throughole PP caps so not sure how valid that is.
Unrelated but adding the Rasmussen filter to this DAC helped hugely, just as advertised the effects were not subtle.
all that was added was 0.1uf in parallel, no resistors, still have to try different values.
I seen that you did something similar with twisted wires close to the ground plane, maybe thats all it takes but id definitely try it out and see.
Someone mentioned you need use SMD caps because inductance of the legs of through hole cap will cancel the effect, I used throughole PP caps so not sure how valid that is.
I did not understand). Will I lose quality as a spdif if the clock is 49.152 MHz? Improvements will be on IIS - USB Amanero? Without register programming, can I safely solder 49.152 MHz?
I ordered on Ali:
1. TPS7A4700 Low Noise Power Module RF Audio Board 3V 3.3V 5V 12V 15V 1A Adjustable-in Integrated Circuits from Electronic Components & Supplies on Aliexpress.com | Alibaba Group spm = a2g0s.9042311.0.0.24e133edazlXXX - to power the analog part.
2. 1PC LM317 Adjustable Regulated Rectifier Filter Power Supply Board Module-in Voltage Regulators/Stabilizers from Home Improvement on Aliexpress.com | Alibaba Group - for power regulation digital part. From a separate transformer winding.
3. TPS7A4700 Low Noise Power Module RF Audio Board 3V 3.3V 5V 12V 15V 1A Adjustable-in Integrated Circuits from Electronic Components & Supplies on Aliexpress.com | Alibaba Group spm = a2g0s.9042311.0.0.24e133edazlXXX - to power the AVCC, for each separately. And for power hours. Total ordered 3pcs.
4. 1 piece opa1612 Double op amp for dac headphone amplifier OPA1612AID patch to pin -in Operational Amplifier Chips from Consumer Electronics on Aliexpress.com | Alibaba Group - для распайки выхода I/V
5. Lusya AK4137 I2S/DSD Sample Rate Conversion Board Supports PCM/DSD Interchange Supports DOP Input -in Amplifier from Consumer Electronics on Aliexpress.com | Alibaba Group - while I will not order. First, I decide what clock I will put 100 or 49 MHz. And what should I do next ...
The ASM1117 controller will not be removed to power the logical part. Film 10 + 10 + 22 + 33 + 33 I will try to pick up from the Soviet. I would certainly like to leave the control from the Apple console. But if you put AK4137 to reduce jitter, then this possibility will disappear. Therefore, let us listen so far - it is interesting how ES9038q2m will sound after the modifications.
I repeat. I have Amareno https://www.aliexpress.com/item/Lus...usb-IIS-Support-DSD512-32bit/32868789488.html ? spm = a2g0s.9042311.0.0.100233eddSBtcv. And I don’t know how the 49.152 MHz clock will work with it.
I ordered on Ali:
1. TPS7A4700 Low Noise Power Module RF Audio Board 3V 3.3V 5V 12V 15V 1A Adjustable-in Integrated Circuits from Electronic Components & Supplies on Aliexpress.com | Alibaba Group spm = a2g0s.9042311.0.0.24e133edazlXXX - to power the analog part.
2. 1PC LM317 Adjustable Regulated Rectifier Filter Power Supply Board Module-in Voltage Regulators/Stabilizers from Home Improvement on Aliexpress.com | Alibaba Group - for power regulation digital part. From a separate transformer winding.
3. TPS7A4700 Low Noise Power Module RF Audio Board 3V 3.3V 5V 12V 15V 1A Adjustable-in Integrated Circuits from Electronic Components & Supplies on Aliexpress.com | Alibaba Group spm = a2g0s.9042311.0.0.24e133edazlXXX - to power the AVCC, for each separately. And for power hours. Total ordered 3pcs.
4. 1 piece opa1612 Double op amp for dac headphone amplifier OPA1612AID patch to pin -in Operational Amplifier Chips from Consumer Electronics on Aliexpress.com | Alibaba Group - для распайки выхода I/V
5. Lusya AK4137 I2S/DSD Sample Rate Conversion Board Supports PCM/DSD Interchange Supports DOP Input -in Amplifier from Consumer Electronics on Aliexpress.com | Alibaba Group - while I will not order. First, I decide what clock I will put 100 or 49 MHz. And what should I do next ...
The ASM1117 controller will not be removed to power the logical part. Film 10 + 10 + 22 + 33 + 33 I will try to pick up from the Soviet. I would certainly like to leave the control from the Apple console. But if you put AK4137 to reduce jitter, then this possibility will disappear. Therefore, let us listen so far - it is interesting how ES9038q2m will sound after the modifications.
I repeat. I have Amareno https://www.aliexpress.com/item/Lus...usb-IIS-Support-DSD512-32bit/32868789488.html ? spm = a2g0s.9042311.0.0.100233eddSBtcv. And I don’t know how the 49.152 MHz clock will work with it.
Next week a few of us are going to Joe's (Rasmussen) place, catch up and have a listen to his highly modded Oppo. There will also be a Modwright top line Oppo to compare.
Joe's Oppo has some fairly controversial mods including the SAW oscillator and super low LF noise supply. Interestingly the SAW resonator doesn't actually measure that good WRT low Freq phase noise.
Not sure what oscillator the Modwright uses. I'll have a good peak.
T
For a simple good sounding USB or RPi hat dac, I would agree two clocks in sync mode is a good solution. Not so good, if SPDIF support is a requirement. Although, the the dac may revert to async mode if switched to its own SPDIF port. If an external SPDIF receiver were used then it could be a problem unless an external ASRC is added, or register programming is switched to async mode.
Regarding using .1uf for a so-called Rasmussen cap (he didn't think of it first, but he did popularize it here at diyaudio), that's way too big, IMHO. Chances are you have made a tone control in the upper audio band, and added significant phase shift. So, no surprise if the effect was a drastic change. Usual starting value is 2,000pf, then adjust up or down some if needed. The idea is to help attenuate any RF leakage from the dac from affecting I/V amp linearity. Best to monitor HD while trying changes. Twisting and routing of wires close to ground plane seems to take care of most of it, but maybe I will come back later and see if a bit more would be better. Regarding parasitic ESL in caps and vias, using tiny SMD caps and the minimum required value of capacitance is necessary for keeping self-resonance-caused wild impedance variations vs frequency from interfering with the filtering effect at RF frequencies.
Regarding using .1uf for a so-called Rasmussen cap (he didn't think of it first, but he did popularize it here at diyaudio), that's way too big, IMHO. Chances are you have made a tone control in the upper audio band, and added significant phase shift. So, no surprise if the effect was a drastic change. Usual starting value is 2,000pf, then adjust up or down some if needed. The idea is to help attenuate any RF leakage from the dac from affecting I/V amp linearity. Best to monitor HD while trying changes. Twisting and routing of wires close to ground plane seems to take care of most of it, but maybe I will come back later and see if a bit more would be better. Regarding parasitic ESL in caps and vias, using tiny SMD caps and the minimum required value of capacitance is necessary for keeping self-resonance-caused wild impedance variations vs frequency from interfering with the filtering effect at RF frequencies.
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The parts you have ordered should be helpful. I don't see a basic problem offhand.
You can use a 49MHz clock without worry with SPDIF. The clock frequency only sets a limit on the maximum sample rates the dac can support, but all SPDIF sample rates will be okay (since they are not too high anyway). It is more important to have an ultra-low jitter or ultra-low phase noise clock than it is to have a low frequency clock (if using a single clock). The reason for going to lower clock frequencies is because ultra-low phase noise clocks have better specs at lower frequencies.
AK4137 can be used to good benefit without register programming, but for best results, with or without an AK4137, register programming would be needed. For example, harmonic distortion compensation can help improve sound quality, but register programming is required.
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Joe stated a cutoff frequency below 20khz and that the special ''effect'' is more than HF suppession and not fully understood, some others mention the ''effect'' being worth the cost of the high treble.
I did add the cap to one channel at first and compared in mono, there was very little affect on HF, most of the effects being similar to what Joe described
but a smaller cap might do exactly the same thing, ill try it out.
I got cheap 2MHz scope recently, not sure if that will be any help here.
btw the unbalanced output with proper filtering was used for this, didnt do much with the balanced output since, its still only passively filtered.
I did add the cap to one channel at first and compared in mono, there was very little affect on HF, most of the effects being similar to what Joe described
but a smaller cap might do exactly the same thing, ill try it out.
I got cheap 2MHz scope recently, not sure if that will be any help here.
btw the unbalanced output with proper filtering was used for this, didnt do much with the balanced output since, its still only passively filtered.
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If your dac is in good shape all the way around, I don't think a big cap there is the right fix. Certainly, ESS evaluation boards don't have that. The ultimate fix for Sabre dacs is something like Benchmark did with DAC-3. We're starting to look into the last issue we need to fix in order to really close in on that level of performance.
Don't know what the LF noise was about, unless it was in reference to AVCC. Any noise, even broadband resistor noise is good to keep low for that. Whatever there is other than pure DC on AVCC it will form IMD and noise with the audio. That's because AVCC has zero PSRR, and the audio signal out of the dac is multiplied by AVCC.
Don't know what the LF noise was about, unless it was in reference to AVCC. Any noise, even broadband resistor noise is good to keep low for that. Whatever there is other than pure DC on AVCC it will form IMD and noise with the audio. That's because AVCC has zero PSRR, and the audio signal out of the dac is multiplied by AVCC.
Hi Guys,
It looks like we have maybe only 3 votes to start a new thread for my ES9038Q2M board project interpolation filter. If so, it doesn't look like enough people keep an active community going just for that.
By the way, I had a problem with the computer running linux that I wanted to use for Vivado, and basically nuked it and had to start over. Vivado didn't like the Ubuntu environment because there were remnants of an old ISE installation there that put stuff in some of the system files, and that caused conflicts keeping Vivado from starting. Its up and running again now with a fresh OS. Have to start on getting Vivado installed after a break.
Also, there are some interesting books I might mention. One is called, "Digital Signal Processing with Field Programmable Gate Arrays," and is available in 4 different editions. There is different material in each edition, and the stuff more applicable to interpolation filters is more in the 2nd and maybe to lesser extent the 3rd edition.
The other book is, "DSP: Designing for Optimal Results," with a subtitle of, "High-Performance DSP Using Virtex-4 FPGAs." It is a Xilinx book that covers more FPGA FIR filter topologies than are described in the Xilinx DSP University material. It would be recommended to have a preexisting understanding of how to interpret the Sigma and Z notation forms used to describe discrete filters before digging into the above books. Same goes for 'Signal Flow Graphs.' If not familiar with those three things, then the "Xilinx DSP University"material would probably be a better place to start.
It looks like we have maybe only 3 votes to start a new thread for my ES9038Q2M board project interpolation filter. If so, it doesn't look like enough people keep an active community going just for that.
By the way, I had a problem with the computer running linux that I wanted to use for Vivado, and basically nuked it and had to start over. Vivado didn't like the Ubuntu environment because there were remnants of an old ISE installation there that put stuff in some of the system files, and that caused conflicts keeping Vivado from starting. Its up and running again now with a fresh OS. Have to start on getting Vivado installed after a break.
Also, there are some interesting books I might mention. One is called, "Digital Signal Processing with Field Programmable Gate Arrays," and is available in 4 different editions. There is different material in each edition, and the stuff more applicable to interpolation filters is more in the 2nd and maybe to lesser extent the 3rd edition.
The other book is, "DSP: Designing for Optimal Results," with a subtitle of, "High-Performance DSP Using Virtex-4 FPGAs." It is a Xilinx book that covers more FPGA FIR filter topologies than are described in the Xilinx DSP University material. It would be recommended to have a preexisting understanding of how to interpret the Sigma and Z notation forms used to describe discrete filters before digging into the above books. Same goes for 'Signal Flow Graphs.' If not familiar with those three things, then the "Xilinx DSP University"material would probably be a better place to start.
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Actually, interpolation filters like we need are FIR filters, but they upsample 8x too. Zero stuffing is used, and there are trade offs in terms of minimizing numerical errors vs keeping computational costs low. 8x could be done all at once, or 2x -> 2X -> 2x, or 4x -> 2x (or the last one in the opposite order). Then there is the issue of I2S having two channels. Should we use the same physical filter for both, but shuffle samples for one channel into memory, bring the last processing samples for the other channel out of memory and load them in the filter to get it ready to start on the new incoming samples, or should we separate the two channels and process them in parallel. And what Signal Flow Graph form of FIR filter would be most suitable. There are performance trade offs depending on number of taps, etc. Lots of things to think about. So, maybe chapter 5.1, too.
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