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Old 19th June 2018, 04:47 PM   #1521
wushuliu is offline wushuliu  United States
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Originally Posted by Markw4 View Post
But, for some of these DIY projects we don't have a lot of expensive gear so we have to use the best methods we can come up with under the circumstances. Fooling one's self can be pretty hard to avoid of no measurement equipment and no reference DAC for comparison either. In that case and if interested in accuracy probably the best we can do is follow good advice of the manufacturer, measurements by people who are equipped to do them, and follow good engineering practices such as proper layout, use of ground planes where indicated, proper power pin bypassing, and so on, etc. That's how I like to approach it anyway.
In that case, shouldn't you be using an ES9028Pro-based board for modding since that's what your reference DAC uses? I have seen no indication so far that the 9028q2m is the same chip.
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Old 19th June 2018, 06:05 PM   #1522
Markw4 is offline Markw4  United States
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Originally Posted by wushuliu View Post
In that case, shouldn't you be using an ES9028Pro-based board for modding since that's what your reference DAC uses? I have seen no indication so far that the 9028q2m is the same chip.
Doesn't seem like it should be a problem. What the reference DAC uses internally is of no concern. It could be a black box. For now, DAC-3 is still SOA in terms of measurements and SQ. As the years go by the bars may be raised, but its fine for now. More than fine, really.

Also, according to ESS Q2M is pretty close to the same a PRO chip. It can play the same formats, operate in the same modes as PRO (for 2 channels, that is). It has 2dB worse distortion specs (-120dB vs -122dB), and mostly differs in terms of noise specs. Q2M can do -122dB and PRO can do as low as -128dB (IIRC), according to ESS. Low noise is from some combination of PRO being able to parallel channels for noise reduction and perhaps lower internal source resistance for the DAC outputs (which you might expect from the higher AVCC currents).

Last edited by Markw4; 19th June 2018 at 06:14 PM.
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Old 19th June 2018, 06:38 PM   #1523
Markw4 is offline Markw4  United States
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Originally Posted by freezebox View Post
Is it just putting a schmitt-trigger chip into signal path between clock and DAC?
I compared Crystek with NDK - NDK has rise/fall time of 6ns and crystek CCHD 575 2ns. What would be a "low value" achievably with a Schmitt Trigger circuit?
It depends. At high frequencies clocks start to look a lot more analog than digital, at least in some ways. A couple of the bigger factors include slew rate into capacitance (how fast can a device charge up a particular load capacitance), and however much the voltage needs to swing before a high or low level is considered to be arrived at, which would be whatever the load device needs.

Roughly speaking in this situation a 2ns spec is good. However, at 100MHz, one cycle takes 10ns. ESS would like to see 4.5ns high and 4.5ns low. That leaves 0.5ns for each edge transition. By that reasoning Crystek should fail to meet the spec. Various possibilities exist. Maybe Crystek beats their spec into the whatever the Q2M load is. Maybe at some voltage level Q2M considers the edge transition complete when the level has changed by only 200mv or some small number, I don't know. Maybe some other possibility. Hard to say without some work and some test equipment.

Seems like for a one-off project the Crystek part makes a lot of sense, at least given all the other stuff that needs work to get the best out of these DACs. Someone could always go back and run some clock buffer experiments later to satisfy curiosity and maybe to try to give back something to the DIY community for the next builders that come along.

Last edited by Markw4; 19th June 2018 at 06:48 PM.
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Old 19th June 2018, 06:53 PM   #1524
Markw4 is offline Markw4  United States
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Also, according to ESS Q2M is pretty close to the same a PRO chip.
Want to make clear I was only talking about ES9038Q2M vs ES9038PRO. Don't know much about 9028Q2M, or whatever the part was K2M?.

Last edited by Markw4; 19th June 2018 at 06:55 PM.
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Old 19th June 2018, 08:49 PM   #1525
freezebox is online now freezebox  Germany
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Mark, so rise/fall time is pending on clock frequency? And the closer the clock is to 4.5ns the better (coming from below this value)? So crystek cchd 975 has 3ns and would be a better choice than cchd 575 with 2ns for this ess dac?
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Old 19th June 2018, 09:09 PM   #1526
wushuliu is offline wushuliu  United States
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Originally Posted by freezebox View Post
Is it just putting a schmitt-trigger chip into signal path between clock and DAC?
Possibly. This is why I referred to cdsgames because their input would be helpful. They have been working on their ess dac for about 8 months, so if they recommend a schmitt trigger maybe there's a reason. My Hifimediy ES9038Pro dac also appears to have a schmitt trigger between clock and dac. And the Quanghao/Andrea dac *also* refers to a 'high speed buffer' between clock and dac. And the Quanghao uses Crystek clocks. So is there something going on there we are not considering if they've all chosen that route?
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Old 19th June 2018, 09:09 PM   #1527
Markw4 is offline Markw4  United States
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@freezebox, Not sure what you are asking about re rise/fall and frequency.

4.5ns is a minimum hold time ESS would like to see for a high or a low. However, to say Crystek has 3ns is not enough information to specify everything that might matter. Clocks are are not perfectly square-shaped as a function of time. Nor are they perfectly trapezoidal-shaped. Those things are approximations to what a real analog clock looks like.

Depending on what is important for a particular application, various things can be specified. ESS doesn't specify much, so its hard to know what really matters for them without doing some tests and measurements. Please see diagrams below for some things that are sometimes specified for pulses and clock-type signals.
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File Type: gif Pulse2.gif (7.4 KB, 154 views)
File Type: jpg Pulse3.jpg (8.8 KB, 155 views)

Last edited by Markw4; 19th June 2018 at 09:15 PM.
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Old 19th June 2018, 09:23 PM   #1528
Markw4 is offline Markw4  United States
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Originally Posted by wushuliu View Post
And the Quanghao uses Crystek clocks. So is there something going on there we are not considering if they've all chosen that route?
Hard to say. Depends if they all really know what they are doing and have the test equipment to do it right. To know what a clock looks like would take an oscilloscope, I think we all understand that. However, scopes have bandwidth limitations and input capacitance, etc., which can produce distortion in what is seen on the screen. A 1GHz or faster vertical bandwidth scope with low-capacitance active probes would help. Probably best to monitor DAC performance when it is connected to see if trying to measure is changing what is being measured.

Also possibly handy to know is that these DACs can be programmed to output MCLK on a GPIO pin. MCLK is derived from XI, which is the real clock or crystal signal. But MCLK might worth looking at with a good scope while doing buffer tests, particularly if the divisor is set to 1. Think I will leave off there.

Last edited by Markw4; 19th June 2018 at 09:28 PM.
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Old 19th June 2018, 10:06 PM   #1529
freezebox is online now freezebox  Germany
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Originally Posted by Markw4 View Post
@freezebox, Not sure what you are asking about re rise/fall and frequency.

4.5ns is a minimum hold time ESS would like to see for a high or a low. .

above you write for a 100 MHz clock one period is 10ns. So to get 4,5ns hold time the rise/fall time must be 0,5ns each. If I use e.g. a 50 MHz clock, the period is 20ns, so rise and fall time could be 11ns in sum to still have 4,5ns hold time? So the necessary "rise/fall speed" is pending on clock frequency?
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Old 19th June 2018, 11:32 PM   #1530
Markw4 is offline Markw4  United States
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So the necessary "rise/fall speed" is pending on clock frequency?
Maybe. What is allowable may vary. If they only specify minimum high or low times and some duty cycle limits, then that could allow for the possibility of slower transitions at lower frequencies. Assuming they have actually specified everything that is important.

If they happen to Schmitt trigger the clock/crystal input inside the DAC chip it may not matter too much so long as the rise and fall characteristics of the clock are extremely repeatable and stable from cycle to cycle. If the slopes or edge transition start/stop times vary from cycle to cycle at all then that would presumably introduce jitter.

Also, allowing any noise pick up during the rise and fall times could also increase jitter.

Last edited by Markw4; 19th June 2018 at 11:34 PM.
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