Hi all,
I have been working on a new RISCV audio processor targeting Artix FPGAs.
The RISCV core has been custom designed and extended with new custom MAC audio instructions. A new octal MAC instruction adds a 48-bit audio pipeline with 80-bit accumulators.
A register file holds 38,400 30-bit filter coefficients in 6.24 format. This register file can store for example 8 channels worth of coefficients each with 4,800 coefficients making processing filter taps on 8 channels simultaneously/ sequentially in as few cycles as possible. At 250Mhz would give a potential 2.0GMACs.
A new configurable i2s, TDM and DSD interface has been designed from the ground up. Each interface supports up to i8s or 64ch TDM. Two external master clocks are used for timing with internal dividers. Each interface can use the system clock via FPGA PLL or either of the two external clocks. There can be as many interfaces as required and FPGA I/O allows. Each audio interface has sample FIFOs that can be monitored from the drivers.
The SoC will support TinyCore Linux and Zeyphr.
Technical details to follow in November. Watch this space!
I have been working on a new RISCV audio processor targeting Artix FPGAs.
The RISCV core has been custom designed and extended with new custom MAC audio instructions. A new octal MAC instruction adds a 48-bit audio pipeline with 80-bit accumulators.
A register file holds 38,400 30-bit filter coefficients in 6.24 format. This register file can store for example 8 channels worth of coefficients each with 4,800 coefficients making processing filter taps on 8 channels simultaneously/ sequentially in as few cycles as possible. At 250Mhz would give a potential 2.0GMACs.
A new configurable i2s, TDM and DSD interface has been designed from the ground up. Each interface supports up to i8s or 64ch TDM. Two external master clocks are used for timing with internal dividers. Each interface can use the system clock via FPGA PLL or either of the two external clocks. There can be as many interfaces as required and FPGA I/O allows. Each audio interface has sample FIFOs that can be monitored from the drivers.
The SoC will support TinyCore Linux and Zeyphr.
Technical details to follow in November. Watch this space!
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About 500 man hours has gone into this so far. I've hired a Linux developer to write drivers for me. Fingers crossed I'll show a video of this all working on Arty soon. If I can get a few substantial donations I'll probably release before Christmas on MIT or similar terms. Well, the core, instructions, compiler diff and i2s/tdm/dsd AXI modules.
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Verification completed on my home brew AXI i2s/tdm/dsd interface. Spec of that peripheral to follow.
The SoC and verification has been completed with a single RISCV core, JTAG, 8 audio interfaces (up to 8ch i2s each) , 2 x UART, i2c and 6 GPIO.
Zephyr support in progress. I2S API recently appeared in v1.9. Alternatively looking at a tiny-fied full Linux kernel.
The SoC and verification has been completed with a single RISCV core, JTAG, 8 audio interfaces (up to 8ch i2s each) , 2 x UART, i2c and 6 GPIO.
Zephyr support in progress. I2S API recently appeared in v1.9. Alternatively looking at a tiny-fied full Linux kernel.
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Small update. Added ...
-- PLIC & DMA controller
-- 8 co-processors to my RISCV core to handle biquad / FIR calcs. Each co-procosor is assigned a RISCV instruction , command and payload and includes literals in C. The coprocessors have a 56-bit fix point datapath, 32-bit coeffs (registers for 21 x 5 x 32b) and 96-bit accumulation. Final result from upto 21 cascaded filters per coprocessor can be truncated to 48, 32, 24bits and stored to a memory address.
---Zepyhr support progressing.
-- PLIC & DMA controller
-- 8 co-processors to my RISCV core to handle biquad / FIR calcs. Each co-procosor is assigned a RISCV instruction , command and payload and includes literals in C. The coprocessors have a 56-bit fix point datapath, 32-bit coeffs (registers for 21 x 5 x 32b) and 96-bit accumulation. Final result from upto 21 cascaded filters per coprocessor can be truncated to 48, 32, 24bits and stored to a memory address.
---Zepyhr support progressing.
What filter types are you using? Just curious, why bother implementing them in software on an FPGA? You've made life more complex by implementing a softcore that's going to be a cheaper and faster if you just bought a hardcore DSP. Or just implement the filters in the FPGA fabric, it's dead easy. I've already done it 6 x 2000 tap FIRs will be give you 384db slope filters - more than enough. All fits into a £20 FPGA, too.