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Arduino controlled dual mono AK4490 DAC
Arduino controlled dual mono AK4490 DAC
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Old 13th June 2017, 10:37 AM   #41
AIM65 is offline AIM65  France
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Join Date: Feb 2015
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Arduino controlled dual mono AK4490 DAC
Hello Lemon,

There's something strange with my DIyAudio thread list : I've received a mail notification of your last post , copied here :

"Cris, Potato Semi is.

I done a quickly test, after the correction of RC (100R, 100p).
I see that is worse now, the FFT unlock occurs more frequently and delays a lot to stabilized.
I have attached two captures, a bclk PO74G74A input and after the PO74G74A (output), with the modification of RC.
I see a delay (second pulse at the same time) of 10 ns, if you see at the video of post#2 this delay was 20ns
."

But I do not see it in the thread list, last post in DimDIm #40 and previous is mine yesterday evening #39. Am I the only one not seeing your post ?
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Old 13th June 2017, 10:40 AM   #42
lemon is offline lemon  Greece
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Dimitri, nice explanation.
In the meanwhile I have done some test with the RC mods.
I tried R values from 0R to 180R with the same 100p to ground.
The bclk different period not change at all.
I don't see any improvement, the all of thing issue is random completely.
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Old 13th June 2017, 10:43 AM   #43
lemon is offline lemon  Greece
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Chris, it was a wrong post, from different output (buffer)...please don't think nothing about this... forget it!

I forgot to say that the chip is Potato Semi, also.

Last edited by lemon; 13th June 2017 at 10:45 AM.
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Old 13th June 2017, 10:43 AM   #44
AIM65 is offline AIM65  France
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Join Date: Feb 2015
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Arduino controlled dual mono AK4490 DAC
Quote:
Originally Posted by Dimdim View Post
I'm a little behind on my part of the testing, but I did take a closer look at this "delay" of the BCLK coming out of our flip-flops.

It turns out that it is not a delay - it's just that some of the pulses have different period than others. This manifests itself like the "delayed" signal seen in lemon's screengrab.

Look at these two videos:

https://www.youtube.com/watch?v=nVRuWlQ5chY

https://youtu.be/YGXnZuIOqVE

Both of them are of the BCLK after its flip flop. The first one is of a 44.1K SR, the second one of 192K SR.

Notice how things change as I move the wave on the x and y axis.

I believe that this issue must be investigated and sorted out first.

Also, look at this capture of the I2S signal both before (channels 0, 1, 2) and after the flip flops (channels 4, 5, 6). Ignore channel 3, it was supposed to be the MCLK but my logic analyzer has nowhere near the required bandwidth to capture it properly:

https://ibb.co/j2u7oQ

This was done on an unpopulated dual ak4490 board, with just the flip flops for one channel soldered on. Signal source was an Amanero, MCLK was the Amanero's.

It seems that the signal is OK in that the LRCK does start at the falling edge of BCLK.

Also the reclocking seems to be helping the DATA signal.

In this case, the BCLK looks OK on the oscilloscope. No "ghosting" or anything.

But, what you are looking at is the beginning of the capture. After a few seconds things might be different - I didn't think to capture several seconds af data and scroll down a few seconds to see what happens. That is on my to-do list.

Yes, I definitely agree, this is not a delay (see post #28).
I miss time to carefully read your post, It should be allright tonight.
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Old 13th June 2017, 09:37 PM   #45
AIM65 is offline AIM65  France
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Join Date: Feb 2015
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Arduino controlled dual mono AK4490 DAC
About the 44.1kHz video :
It looks like the period (T) of the signal is constant and is close to 360nS which is consistent with expected value for BICK : 44.1KHz*32*2 bits/frame = 2.8224 Mb/s; bit period =1/2.8224M = 354nS.
As said, sometime BICK high level duration is T/2 which is expected behavior, and sometime high level duration th=T/2 + 20ns close to 380nS while tlow=T/2 - 20nS. This 20nS value is clearly measurable on the 192KHz video.
Assuming you run at 8x oversampling, MCLK is 8*2.8224 Mb/s = 22.5792 MHz; period = 44.28nS.
It looks like sometime, on rising edge of MCLK the D flipflop latch a zero and sometime it latch a 1. This may occurs when D input and CK input change at the very same time without having a setup time on D before clock rise. But this is weird because in that case we should have a variation of th equal to the period of the clock (44.28nS) and we’ve got half !. Maybe what we see on scope is not what really happen and it’s a syncing issue, a faster protocol analyzer would be helpful…
But, to be sure, could you confirm frequency of MCLK ?

If I may, some interesting measures with scope could be the following :
  • A channel : BICK at input of the D , B channel : BICK at output of the D, Sync: rising edge of A then falling edge in order to cross check. That should allow to understand how D input is reproduced on output, the additional duration of high should be visible
  • If you have a C channel add MCLK, if not : A channel : BICK at input of the D, B channel : MCLK, Sync rising edge of A. 8 clock period of MCLK should be visible per BICK period, we should look at when rising edges of MCLK occurs around BICK changes, this should allow to understand why we have variation of high level time (th).
At the end if it’s confirmed that MCK rising edge if too close BICK rising edge, solution remains to add a delay in MCK.

It's not easy to figure what can go wrong without been able to make some tests ! I still think it’s a clocking issue related to lack of compliance with datasheet (Page 20 note 21) and respect of tSDS and tSDH. If you look at I2S timing on page 33 (mode 3 timing) you’ll see LRCK changing on falling edge of MLCK and Data sampled on rising edge (see text in previous page). You can get close to this by trying to invert MCLK of the BICK D latch only.

Sorry for being verbose, I’m currently working on an AKM DAC project (without reclocking !) and I still haven’t been working on this side of the chip…simply because I’m using a 4118 which handle this stuff very well.

Chris

Last edited by AIM65; 13th June 2017 at 09:45 PM. Reason: Error in page# for datasheet
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Old 13th June 2017, 10:28 PM   #46
Dimdim is offline Dimdim  Greece
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Arduino controlled dual mono AK4490 DAC
Chris, thank you very much for your time.

I'll take the measurements that you described tomorrow (with a clear head). My oscilloscope is a 4 channel one so I can add the MCLK.

By the way, in my 44.1K video the MCLK is at 45.1584 MHz so that explains the ~20ns period. In the 192K video MCLK is at 49.152 MHz, in both cases generated by my Si570.

Will we get to see your AKM DAC project when it's finished?
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Old 18th June 2017, 11:05 PM   #47
Dimdim is offline Dimdim  Greece
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Arduino controlled dual mono AK4490 DAC
I seem to have made some progress.

I desoldered the Si570 from the board and provided MCLK from my Amanero (22/24MHz clocks).

The "ghosting" of the BCLK went away, proving that it was indeed an "artifact" of the different clock domains between the DAC board and the I2S source board.

Also, the "unlocks" went away as well, at all sampling rates and frequencies.

However, I am still a little worried about the timing between the BCLK and the LRCK.

Looking at these grabs, Input 4 (first trace from the top) is BCLK before the flip-flop, Input 2 (second trace from the top) is BCLK after the flip-flop, Input 3 (third trace from the top) is LRCK before the flip-flop, Input 1 (last trace from the top) is BCLK after the flip-flop.

44.1KHz:
Arduino controlled dual mono AK4490 DAC-flip-flop-amenero-44-1k-png

88.2KHz:
Arduino controlled dual mono AK4490 DAC-flip-flop-amenero-88-2k-png

172.4KHz:
Arduino controlled dual mono AK4490 DAC-flip-flop-amenero-176k-png

192KHz:
Arduino controlled dual mono AK4490 DAC-flip-flop-amenero-192k-png

It looks to me like at some frequencies the LRCK after the flip flops is delayed a little too much, especially in case of the 192K SR. It looks like it's almost gotten to the leading edge of BCLK, which should be a problem. However, the DAC does not seem to mind.

Don't pay too much attention to how clean the traces look - grounding was a mess while I was doing my tests.

One last thing, with the Amanero's MCLKs I couldn't get the flip-flops to do their work for 352K+ SRs but that is to be expected.. I'll also do tests with other I2S sources, ones that have faster MCLKs.

Your thoughts?
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Old 19th June 2017, 12:16 PM   #48
lemon is offline lemon  Greece
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Just, I tried the same method like Dimitris.
I feed with amanero mclk the AK board and the rest of i2s signal are coming from the Acko S03 board normally.

All the "unlocks" went away as well, at all sampling rates and frequencies like Dimitris but I have no any lucky with the "ghosting" of the BCLK pulse that remains with a random "ghosting" delay of 20-22ns depends from the music sampling.
I have included 48/192K captures for this purpose.

I repeat the same for the LRCLK, with capture before and after flip-flop but I don't see the same delay as Dimitris. I have included 48/192K captures for this purpose.

At 352/384K sampling files, the "ghosting" pulse (bclk) is major and at random times covers 2 or 3 pulses with opposite phase or same phase (it is very complicated to captured in photo, only with a video). This is the reason that we can't to reproduce these sampling music files with the reclocking flip-flops.
Attached Images
File Type: png BCLK 48K.png (20.1 KB, 43 views)
File Type: png BCLK 192K.png (22.7 KB, 48 views)
File Type: png LRCLK 48k.png (18.5 KB, 43 views)
File Type: png LRCLK 192k.png (19.1 KB, 42 views)
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Old 19th June 2017, 02:13 PM   #49
lemon is offline lemon  Greece
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Hmm, I see that Dimitris applied re-clocking pulse to flip-flops from amanero mclk, also...that I didn't applied!
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Old 19th June 2017, 07:26 PM   #50
lemon is offline lemon  Greece
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Join Date: Apr 2009
We have a good news.
As the problems occur due to double clock domains, we tried to flash at slave mode the amanero board.
Now the two external clocks of Acko S03 board drive the mclk signal into the Xilinx CPLD of Amanero and all system has one clock domain.
The same can be applied by Si570, also.

With this setup there is no any FFT signal unlocking and all the sampling files from 44.1-384KHz play well.
The BCLK "ghosting" delay pulse has gone, also.

Summary, with the Amanero slave mode all the problems resolved and the Flip-Flop technique works fine.

Thanks to all for the encourage.
Attached Images
File Type: jpg thd_2.jpg (165.9 KB, 63 views)
File Type: png bclk 48K.png (11.9 KB, 64 views)
File Type: png bclk 88K.png (11.7 KB, 46 views)
File Type: png bclk 96K.png (11.8 KB, 41 views)
File Type: png bclk 192K.png (12.5 KB, 41 views)
File Type: png bclk 352K.png (12.5 KB, 42 views)
File Type: png bclk 384K.png (12.6 KB, 45 views)
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