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Old 6th June 2017, 06:55 PM   #21
lemon is offline lemon  Greece
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AIM65 please read the post #19, we have tried with reclock with the clock provided by ours i2s source, also.
Except you meant, that the pulse that introducing into the flip-flop chips not to be the external clocks but the same amanero's mclk.
In my setup, I can tried it easily.
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Old 6th June 2017, 07:01 PM   #22
AIM65 is offline AIM65  France
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Quote:
Originally Posted by Dimdim View Post
I can try that, even though I've checked the MCLK both at its source (Si570) and on the 4490's pin and they look pretty much identical.

The 4490s appear to be pretty tolerant of the MCLK. I've tried MCLKs starting at ~11MHz (the lowest specified) with no change. Manolis even tried a 3MHz signal that he had available, and the 4490 still produced sound (even though it had a lot of THD..). Even with a completely wrong MCLK, the chip works, even though the THD increases to over 3%.



You mean to put a 50R resistor before each flip-flop, plus keep the R4 resistors, right?

Information on proper termination of signals of this kind is kindda sketchy.. I've done a lot of reading and I still haven't got a proper grasp on it.

In case of the resistors before the flip-flops, shouldn't the termination be of "parallel" type? Via resistors to gnd? But since the source of the I2S signal will be "seeing" two resistors in parallel, it will be seeing half the resistance. But an even better way to go about it would be to buffer & split the signals properly. But that adds jitter. And so on, and so forth..

So I just left the signal as it was, improperly terminated. The pulses look just fine on the ol' scope, so it should be working OK.



We've tried both with the Si570 and without, with MCLK coming either from Acko's reclocker or directly from the Amanero with the same results. What I haven't tried (and I believe neither has Manolis) is Acko's reclocker on a single-4490 board with no reclocking. But I might be mistaken.. He'll let us know.



See above, they are not, but that doesn't seem to impact the shape of the pulses.

I will try the inversion of the MCLK.
This is not a question a termination, termination issue is for the UFL links, and you right : termination resistors have to be connected to gnd.

The point here is about damping the LC networks formed, at MCLK frequency, by the input cap of the chip (CMOS one) and the pcb layout. This is why we add damping resistors in order to have an RLC with Q factor under control.
My idea was to remove R1 and to have one resistor in serial with MCLK of 4490A and one in serial with MCLK of 4490B (by the way could you post a larger part of the schematic in order to see all the connections of MCLK ?)

About the damping resistor of the 3 D latch : I wouldn't use them, but if you need them it should one in serial per D latch.

About your measurement with the scope : connecting the probe add few pF and may dramatically change the waveform, f0 and Q factor of the LC. The measurement process change the measured value...


Last thing, and I'm not sure this could be another error in AKM documents, on app notes of AK4490 and 4495 the damping resistor of MCLK is 5.1R, not 51R. 51R is for the slower signal : LRCK, BICK and SDATA

Last edited by AIM65; 6th June 2017 at 07:10 PM.
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Old 6th June 2017, 07:03 PM   #23
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I am not sure how this is done in this context. But in synchronous digital circuits, the D input to a flipflop has to be synchronously generated to the clock on the CLK input of the flipflop. Otherwise, this will result in metastability and incorrect sampling.

The two clocks cant simply be of the same frequency, but to be synchronous they have to be from the same source.

Further their phases have to be such that the D input can meet flops setup/hold requirement with respect to the clock input.

Sorry if this doesnt apply in the context of reclocking the I2S stream, i have to read in more details to understand.
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Old 6th June 2017, 07:08 PM   #24
AIM65 is offline AIM65  France
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Quote:
Originally Posted by lemon View Post
AIM65 please read the post #19, we have tried with reclock with the clock provided by ours i2s source, also.
Except you meant, that the pulse that introducing into the flip-flop chips not to be the external clocks but the same amanero's mclk.
In my setup, I can tried it easily.
Hi Lemon,

I've havent' read, I was on my way

That seems to close this direction for seeking a solution....weird.
And I'm not convinced that the damping resistor issue is the solution, but it's not difficult to try !

Chris
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Old 6th June 2017, 07:46 PM   #25
nattawa is offline nattawa  Canada
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Quote:
Originally Posted by Dimdim View Post
The Si570 is not phase locked to anything, just its frequency is adjusted according to the incoming SR by the uC.

It makes sense that periodically things will get out of alignment, and that weird things will happen at that moment, but I didn't expect that to be audible, since this is not the first such implementation in our field.
Then, the si570 that is not phase locked/synced with the I2S sources renders a reclocker operating cross-domain, or non-worky in another words.

In your circuit it is unlikly that there would be a data error, as the data line level transition does not likely take place anywhere near within 20nS around bit-clock transition. However, you most definitely will get a timing error of 20nS every once in a while on both the BCK and LRCK feeding into the AK4490. That would be a huge timing error. I think the response of AK4490 to such timing error has been interpreted as an occasional, sudden noise floor elevation by the FFT measurement as shown in the youtube video clip.

You probably want to ASRC the I2S sources if you insist doing it cross-domain.
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Old 10th June 2017, 05:02 PM   #26
AIM65 is offline AIM65  France
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Default 4490 clocking

During my fly back home last night I had some time to dive back into AKM datasheet and I found something that may be interesting.
In AK4490 datasheet Rev03 it is said that:
  • For PCM, there’s a timing relationship between LRCK and BICK. There are two delays with minimum value which are mandatory. That says that LRCK has to be stable (not changing) 5nS mini before and after BICK rise. See Page21, notes 20 & 21 and Page 23
  • For DSD, DSDL/R should be stable within a windows of -20nS/+20nS around DCLK, See Page21 & 22, notes 22 & 23 and Page 23. Windows size is linked to DSD speed, in DSD256 size is : -5/+5nS
Your relocking method, by design, won’t allow this: LRCK & BICK and DSDL-DSDR / DCLK changes at the very same time: rising edge of MCLK. Your external reclocker ‘Acko’ has certainly the same behavior and you noticed the same issue with it.

In order to comply with these timing requirement, one solution could be to add some delay between the signals. Delaying BICK/DCLK of +25nS should be ok for PCM and for DSD. With 25ns delay the DSDL/R lines are stable when DCLK occurs and as is LRCK regarding rising edge of BICK.

As 74AUP1G79 has Schmitt triggered input, an RC on clock input could be used to provide delay. For 25nS delay , as ViH on the Schmitt trigger =2V, using R=120R and C=220pF should give a delay of approximatively 25nS. Attached picture describe this. Otherwise, some old HCMOS gates could be used as delay source such 74HC04. Such chip, powered at 3.3V should have a propagation delay per gate near 15 nS, two gates should be all right.

If you look at the AK4118 datasheet, which ‘perfectly’ feed the 4490, you’ll notice that it is compliant with those timing requirements.

Maybe you can try this. Better to try with external I2S source MCLK, not with your asynchronous one, at least to qualify the delay issue.

Hope this help

Chris
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Old 10th June 2017, 05:42 PM   #27
lemon is offline lemon  Greece
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Chris, thanks a lot for these information.
Yes, it is easy to tried this RC BCLK delay, but I have a suspicious that there is 20ns BCLK delay (some how) at the the BCLK youtube video at post #2 (I have called like a "ghost pulse").
I don't know if this delay is reclocking sophisticated or random but as you know doesn't work on ours project
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Old 10th June 2017, 06:03 PM   #28
AIM65 is offline AIM65  France
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Quote:
Originally Posted by lemon View Post
Chris, thanks a lot for these information.
Yes, it is easy to tried this RC BCLK delay, but I have a suspicious that there is 20ns BCLK delay (some how) at the the BCLK youtube video at post #2 (I have called like a "ghost pulse").
I don't know if this delay is reclocking sophisticated or random but as you know doesn't work on ours project
I do not interpret the video as a delay on BICK but as a longer high pulse width which maybe the result a many thing : a sudden drop of the frequency of the vcxo (lower freq means longer period : longer high and low level), or a scope artifact, or a bad sync of the scope, etc...
When I debug, I usually try to remove all the peripheral causes of issue before focusing on the main issue. This is why, on your case, I may suggest first to only use a clean, safe and well knows I2S source with its MCLK.
By the way, is your youtube video made with the VCXO or an external MCLK ?

Chris
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Old 10th June 2017, 07:39 PM   #29
AIM65 is offline AIM65  France
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I've done a quick check in LTpsice, RC is too high the D latch input will never see a 0 level, better try with 100p and 150R. Reduce R if Dac stays silent....

Chris
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Old 11th June 2017, 06:34 AM   #30
lemon is offline lemon  Greece
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Quote:
Originally Posted by AIM65 View Post
I...
By the way, is your youtube video made with the VCXO or an external MCLK ?

Chris
This capture was done with Acko S03 board for reclocking and feeding the mclk too.

Last edited by lemon; 11th June 2017 at 06:36 AM.
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