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Old 6th June 2017, 10:36 AM   #11
lemon is offline lemon  Greece
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Thanks for the encourage guys...
Joseph, we dont tried the input inverted pusle signal to the FIFO chips, but we'll tried...

Any suggestion that could to help us, is welcome.
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Old 6th June 2017, 11:19 AM   #12
Dimdim is offline Dimdim  Greece
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We can try that, inverting the MCLK and see if it changes anything.

A good logic analyzer would come in handy here.. It would be nice if we could capture the I2S signals both before and after the flip flops at the moment that the glitch occurs.

I did try to do that in fact, but couldn't manage to capture the exact moment of the glitch.

In my test my logic analyzer showed that the data stream remained bit perfect after the reclocking, though some of the samples were shifted a bit in time (due to the reclocking obviously..).

Anyone know of a good I2S test signal file? It would come in handy..
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Old 6th June 2017, 11:49 AM   #13
nattawa is offline nattawa  Canada
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Not a digital audio expert here but would you be slaving the i2s sources with the si570 as the clock master? Sorry if I have neglected.
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Old 6th June 2017, 12:06 PM   #14
Dimdim is offline Dimdim  Greece
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What is happening is that we are not using the MCLK from the I2S sources at all. We are just getting the BCLK, LRCK & DATA signals and reclocking them with our Si570's clock, which is also used as the AK4490's MCLK.

This tactic is followed by many reclocker projects.
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Old 6th June 2017, 12:39 PM   #15
nattawa is offline nattawa  Canada
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Then, is the si570 phase-locked onto anything? If it is let operate in free run, there will be occasions the D flip-flops get an input transition at its CK and D at the same moment causing output uncertainty, which translates to jitter equivalent to a clock cycle of the MCLK (the si570 puts out).
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Old 6th June 2017, 12:44 PM   #16
AIM65 is offline AIM65  France
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Hi Dimdim, great project.

Some though :

Have you tried to short R1 ? : assuming R4A is connected to MCK of both 4490 there are two RC network between MCLK input and the 2 4490. This may affect slope of MCLK on 4490.

Better implementation is maybe to have one 50R per input (on each D latch and on each 4497) rather than sharing the damping resistor. When sharing it, you sum the caps of each input.

Is it the same Si570 circuitry used when you try with and without the reclocker ? If not, you could consider that the issue is not the reclocker but the delivery of MCLK to the 4497. If I remember well AKM datasheet warns about relationship between MCLK signal and SNR.

Last think, UFL and coax are transmission lined, it may be useful to terminate them by 50 or 75R according your coax. Maybe they are, but it does not appear on the schematic fragment.

Inverting MCLK between the D Latch and the AK4497 is a simple thing to try too.
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Old 6th June 2017, 01:30 PM   #17
Dimdim is offline Dimdim  Greece
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Quote:
Originally Posted by nattawa View Post
Then, is the si570 phase-locked onto anything? If it is let operate in free run, there will be occasions the D flip-flops get an input transition at its CK and D at the same moment causing output uncertainty, which translates to jitter equivalent to a clock cycle of the MCLK (the si570 puts out).
The Si570 is not phase locked to anything, just its frequency is adjusted according to the incoming SR by the uC.

It makes sense that periodically things will get out of alignment, and that weird things will happen at that moment, but I didn't expect that to be audible, since this is not the first such implementation in our field.
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Old 6th June 2017, 02:22 PM   #18
Dimdim is offline Dimdim  Greece
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Quote:
Originally Posted by AIM65 View Post
Hi Dimdim, great project.

Some though :

Have you tried to short R1 ? : assuming R4A is connected to MCK of both 4490 there are two RC network between MCLK input and the 2 4490. This may affect slope of MCLK on 4490.
I can try that, even though I've checked the MCLK both at its source (Si570) and on the 4490's pin and they look pretty much identical.

The 4490s appear to be pretty tolerant of the MCLK. I've tried MCLKs starting at ~11MHz (the lowest specified) with no change. Manolis even tried a 3MHz signal that he had available, and the 4490 still produced sound (even though it had a lot of THD..). Even with a completely wrong MCLK, the chip works, even though the THD increases to over 3%.

Quote:
Originally Posted by AIM65 View Post
Better implementation is maybe to have one 50R per input (on each D latch and on each 4497) rather than sharing the damping resistor. When sharing it, you sum the caps of each input.
You mean to put a 50R resistor before each flip-flop, plus keep the R4 resistors, right?

Information on proper termination of signals of this kind is kindda sketchy.. I've done a lot of reading and I still haven't got a proper grasp on it.

In case of the resistors before the flip-flops, shouldn't the termination be of "parallel" type? Via resistors to gnd? But since the source of the I2S signal will be "seeing" two resistors in parallel, it will be seeing half the resistance. But an even better way to go about it would be to buffer & split the signals properly. But that adds jitter. And so on, and so forth..

So I just left the signal as it was, improperly terminated. The pulses look just fine on the ol' scope, so it should be working OK.

Quote:
Originally Posted by AIM65 View Post
Is it the same Si570 circuitry used when you try with and without the reclocker ? If not, you could consider that the issue is not the reclocker but the delivery of MCLK to the 4497. If I remember well AKM datasheet warns about relationship between MCLK signal and SNR.
We've tried both with the Si570 and without, with MCLK coming either from Acko's reclocker or directly from the Amanero with the same results. What I haven't tried (and I believe neither has Manolis) is Acko's reclocker on a single-4490 board with no reclocking. But I might be mistaken.. He'll let us know.

Quote:
Originally Posted by AIM65 View Post
Last think, UFL and coax are transmission lined, it may be useful to terminate them by 50 or 75R according your coax. Maybe they are, but it does not appear on the schematic fragment.

Inverting MCLK between the D Latch and the AK4497 is a simple thing to try too.
See above, they are not, but that doesn't seem to impact the shape of the pulses.

I will try the inversion of the MCLK.
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Old 6th June 2017, 03:06 PM   #19
lemon is offline lemon  Greece
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Quote:
Originally Posted by AIM65 View Post
Hi Dimdim, great project.

Some though :

Have you tried to short R1 ? : assuming R4A is connected to MCK of both 4490 there are two RC network between MCLK input and the 2 4490. This may affect slope of MCLK on 4490.

Better implementation is maybe to have one 50R per input (on each D latch and on each 4497) rather than sharing the damping resistor. When sharing it, you sum the caps of each input...
Just I tried this.
I short the R1 & R2 with the 0R smd resistor and let only the R4A & R4B (they are the terminal resistors before input AK).
In other worlds, I have two resistors in the signal, one at the side of Acko's reclocker and the other at the end of signal before each AK.

Unfortunately, I have no any lucky with this!

My setup is different from Dimitris but with the same reclocking philosophy. The i2s signal runs from Acko's S03 reclocker, completely. I have no any local master clock on the AK board.
We are quite sure that this issue caused from reclocker side. Before, I have tried the Amenero (without any reclocking) to drive the AK board (dual mono) and everything was OK.
The Acko's S03 has two methods of master clock output. One mclk output relates with Amanero's mclk, this signal runs into the FF and each FF accepted the new clock pulse from the local recloking clocks (the signal is 22/24MHz), the other mclk outpute has no any relation with amanero's mclk because is driven from local reclocking clocks direct (the signal is 45/49MHz).
I have tried both of them, both had the same behavior on FFT.

Last edited by lemon; 6th June 2017 at 03:10 PM.
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Old 6th June 2017, 06:46 PM   #20
AIM65 is offline AIM65  France
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Quote:
Originally Posted by Dimdim View Post
What is happening is that we are not using the MCLK from the I2S sources at all. We are just getting the BCLK, LRCK & DATA signals and reclocking them with our Si570's clock, which is also used as the AK4490's MCLK.

This tactic is followed by many reclocker projects.
Dimdim,

Back from work I had a look the datasheet to confirm something I has in mind : according AKM datasheet (4495,90 & 97), phase of LRCK regarding MCLK doesn't matter BUT they have to be synchronous. That means you should reclock with the clock provided by your I2s source : AK4118 or AK4137, I dont know your setup. I believe you cant't use an arbitrary source even with close frequency, they will never be isochronous unless you sync with a gps...

But that seems to work without the reclocker... Maybe the reclocker influence, which resample the signals, highlight the little freq difference between the I2S source and the VCXO causing some bit loss when loosing a phase (H or L) from LRCK on a MCLK rising edge.
That may explain the relationship between the sampling frequency and the occurrence of the noise floor jump.

Easy way to confirm/infirm this hypothesis : remove the si570 and provide your DAC board with the MCLK out of your 4118.
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