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Old 29th April 2017, 02:27 PM   #1
isiora is offline isiora  Italy
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Join Date: Nov 2009
Location: Salerno
Default ClearPath: an ESS DAC project FPGA based

Hi folks,

I have the pleasure and the excitement to present my first project on the pages of this forum. Its name is ClearPath.
It's a project that I had in mind for a long time, more than 6 years ago, but alas I did not find the time to finalize it before now. It is a DAC, based on the famous ESS chip ES9018 (it could also use the latest ES9038PRO. I still have not tried it, although I signed the NDA and I have the datasheet).
It has the following features:
  • You can connect to the source via SPDIF AES/EBU, asynch USB or Ethernet
  • the analog and digital domains are galvanically isolated
  • the power is inductive, with an upstream shunt regulator (later I will explain why I did this choice)
  • the output can directly control headphones
  • uses a low jitter clock (obviously). I chose to use quartz at 45.1584 and 49.152 MHZ
  • includes a Zynq FPGA with an ARM Cortex-A9 where the programmable logic and firmware resides
  • the usb stack is developed by me, starting from a xilinx driver, as well as the ChibiOS/RT port on Zynq (I'm the coauthor of a ChibiOS anchestor)
  • the TCP/IP stack is now based on lwip2.0, which I ported under ChibiOS
  • the DLNA interface is based on an open stack of Intel, revised and adapted by me (it was tremendously buggy)
The project is fully realized and I'm listening to it while I'm writing these notes.

The Zynq with its ARM has a computing power that can be used to develop an entire very advanced DSP audio.
This is one of the interesting aspects of the project, though it has the cost of the FPGA daughterboard.

The other is given by the particular configuration of the power supply, which is inductive. It is characterized by the fact that L is an energy storage element and it has the following advantages:
  • it avoids current spikes in the rectifiers and in the capacitors during the charging cycle
  • the rectifiers conduct for a whole electrical cycle with a peak current near the average
  • thanks to this, it shows low radio frequency emissions and rectification disturbances, even if it can worsen low-frequency electromagnetic emissions.
  • it keeps virtually constant power impedance from electric network point of view, and the current circulation doesn't adruptly change during network cycle
  • has a marked filter action and the ripple residue has a low harmonic content; it's almost perfectly sinusoidal
  • there is a very low stress of the electrolytic filter capacitors and then it extends their life cycle
The LRC circuit of the inductive power supply however has a self resonance that forces the use of a larger inductor if we want to kept it in the infrasonic area, otherwise the signal current variations in the load at that frequency are reflected, and for a long time, on the output voltage. Here is then the idea of ​​cascading a shunt regulator, placed directly on the DAC board. His job is to guarantee two things: a local circulation on the dac board of all the signal currents, and a constant current in the inductor, so as to avoid resonance excitation. In this way we can use an inductor up to 5-10 times smaller. In the prototype I used 1H inductors, because I already had them, but even 200mH are already enough.

Attached you can see an high level architecture, an image of the board, and a picture of the power supply. The boards are still without a box, and are mounted on wooden bases.
In a next post, while I'm awaiting your impressions, I'll publish the schematics.

Update 1st June 2017
DoP and DoPE decoder added into FPGA. Now the DAC is capable to play DSD64 and DSD128 from USB and DLNA interfaces. The decoding process is done directly into FPGA. That it is independent from the DAC chip and it works with both the ES9018 and the ES9038.

Bye,
Isidoro Orabona
Attached Images
File Type: jpg ClearPathArch.jpg (123.6 KB, 800 views)
File Type: jpg CP.jpg (562.6 KB, 799 views)
File Type: jpg AlimCP.jpg (250.7 KB, 779 views)

Last edited by isiora; 1st June 2017 at 08:43 PM. Reason: New features added
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Old 29th April 2017, 03:14 PM   #2
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Yes please!!!! Sign me up
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Old 30th April 2017, 11:11 AM   #3
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Join Date: Nov 2013
As always, there is a good ES9018 project shown and almost no users are interested to comment.
As a soldering freak, I see some imperfections like blue pots, radiators and some strange bridge at U18 (?). But overall, the board looks very nice. Good you used small caps near the DAC (0402?), but I'd place the bigger caps on left and right a little closer. Although, they are closer than on the Prometheus board :P

How many shunts are there on the board?
I like the fact that the clock path is very short and seems to be not distracted by other signals. If I would change one thing, I'd separate the ground plane for clock signal feeding DAC chip and connect to other ground planes only with chokes.

And, finally someone intends to use the programming good of ES9018 chip with FPGA CPU.
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Old 1st May 2017, 07:40 PM   #4
isiora is offline isiora  Italy
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Join Date: Nov 2009
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surely!
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Old 1st May 2017, 08:34 PM   #5
isiora is offline isiora  Italy
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Join Date: Nov 2009
Location: Salerno
Thank jot23 for your interest and your suggestions.

The 'small caps' are 3 terminals EMIFIL (NFM18PS) in 0603 package. I found them to be more critical than the bigger ones (that are C0G): the EMIFILs are on the 1.2V core vdd, while the C0G on avcc. Therefore in the layout I gave priority to them, and the space has served for the 1.2V plane below them (the board has 4 layers).

There are two shunt, one on each main power rail (+ and -).

The clock has however his own filter with ferrite and emifilters, and yes you are right, no other signal runs close to it.
I don't like those imperfections either (they annoy me). Unfortunately, I had to rework by hand the heatsinks, because of the bad soldering in the reflow oven (they were overzealus in doing their job ).

Last edited by isiora; 1st May 2017 at 08:46 PM.
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Old 4th May 2017, 09:05 PM   #6
isiora is offline isiora  Italy
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Join Date: Nov 2009
Location: Salerno
Default ClearPath DAC schematic and use case

Hi,

I attached the ClearPath DAC schematic, together with a slide showing the DAC used as a DLNA Media Renderer. The schematic pdf has popup menu on the components for the details.

Any suggestion or comment is welcome.

Isidoro
Attached Files
File Type: pdf ClearPathSchematics.pdf (428.0 KB, 174 views)
File Type: pdf ClearPathDMRUseCase.pdf (257.4 KB, 84 views)
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Old 4th May 2017, 10:03 PM   #7
Dimdim is offline Dimdim  Greece
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Join Date: Sep 2008
Location: Athens
Very nice project!

One thing I did notice on the schematic is that you seem to be pulling up the SDA line but not SCL (on the clean side). Is everything working OK regardless of that?
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Old 5th May 2017, 06:50 AM   #8
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really nice work.
Subscribed.
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Old 5th May 2017, 09:21 PM   #9
isiora is offline isiora  Italy
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Join Date: Nov 2009
Location: Salerno
Hi Dimdim,

everything works OK. The Si8602 has an unidirectional channel for SCL made by a standard CMOS input. Therefore the (hidden) pullup that I programmed in the OBUF of the FPGA allows everything to work fine.

Bye,
Isidoro
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Old 8th May 2017, 07:15 PM   #10
bsy020 is offline bsy020  Israel
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Join Date: Oct 2005
Thumbs up Exceptional piece of Engineering work

I'm definitely interested. How did you do all of this all by yourself?
I think the firmware alone is so much work. I would really love to see
it work with ES9038pro.
Thanks for sharing.
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