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Old 20th December 2016, 05:45 PM   #1
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Default S/PDIF and PLL

Hello! First, I apologize for spelling, English is not my native.

I wonder how PLL work with S/PDIF signal. What I mean? Assume that we have 44.1kHz sampling, then actual clock frequency is 44.1 x 32 x 2 = 2.82MHz

Yes but the signal is modulated, and those 2.82MHz would be true if the signal contains only "1". The zeros determine the frequency in half, and preamble 1/3 from the clock. I.e. we can assume that we have random content in the signal, so frequency is constantly changing.

So how PLL in the receiver work with this mess?

Regards!

Last edited by alexandar888; 20th December 2016 at 05:52 PM.
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Old 21st December 2016, 02:53 AM   #2
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The Digital Input Receiver's PLL locks onto the S/PDIF signal's preamble pattern, which is not data dependent. So, while the biphase-mark encoded data still has to be decoded, the recovered clock is not jittered by it. This idea was patented by Ed Meitner back in the nineties, but that patent has now expired. I recall that Cirrus DIR chips have long utilized the idea.
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Old 21st December 2016, 11:51 AM   #3
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I.e. in the upper case, 2.82MHz is the data clock, master clock must be x 2 = 5.64MHz and divided by 6 for preamble (0.94MHz). Is that correct?
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Old 21st December 2016, 02:20 PM   #4
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Since the preamble is synchronous with the received sample rate, once the reciever PLL is locked it can easily generate any master clock frequency that's an integer multiple of that sample rate. Common receiver generated master clock ratios are x128, x256, x384 or x512. Fractional N divider ratio PLL's aren't commonly utilized (the Wolfsen WM880x receivers may, I'm uncertain) in audio DAC input receivers unless that reciever employs an NCO based custom PLL.
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Last edited by Ken Newton; 21st December 2016 at 02:25 PM.
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Old 22nd December 2016, 08:43 AM   #5
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The clock is coded into the signal. From wiki: https://en.wikipedia.org/wiki/S/PDIF:: "S/PDIF is used to transmit digital signals of a number of formats, the most common being the 48 kHz sample rate format (used in DAT) and the 44.1 kHz format, used in CD audio. In order to support both systems, as well as others that might be needed, the format has no defined data rate. Instead, the data is sent using biphase mark code, which has either one or two transitions for every bit, allowing the original word clock to be extracted from the signal itself."

The signal is also coded with a NRZ (none return to zero) scheme making it's DC component being zero. https://en.wikipedia.org/wiki/Differ...ester_encoding

It's a bit more to it than one might think. A shame that the interface wasn't made with one physical link carrying data downstream and one for the clock sent the other direction. But hey, its a consumer standard and need to be cheap.

//

Last edited by TNT; 22nd December 2016 at 08:47 AM.
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Old 22nd December 2016, 03:52 PM   #6
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Quote:
Originally Posted by TNT View Post
...The clock is coded into the signal...the data is sent using biphase mark code, which has either one or two transitions for every bit, allowing the original word clock to be extracted from the signal itself."
Unfortunately, that process also generates significant amounts of data dependent jitter of the recovered clock signal. The preamble based method in Meitner's patent solves that problem.

Quote:
A shame that the interface wasn't made with one physical link carrying data downstream and one for the clock sent the other direction. But hey, its a consumer standard and need to be cheap.
S/PDIF use has evolved to transmit digital audio signals between separated transport and DAC in the home, but it wasn't the originally intended use. I recollect reading that it was originally intended simply as a diagnostic port in integrated CD player manufacturing/repair. As such, jitter on the recovered clock isn't of concern, so long as it isn't so severe as to provoke actual bit errors. I believe it was Arcam who first utilized the port to connect an external DAC, back in the late eighties.
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Last edited by Ken Newton; 22nd December 2016 at 04:18 PM.
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Old 22nd December 2016, 05:20 PM   #7
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Is it possible to construct preamble detector from logic gates (discrete) ?

I do something similar to oversampling S/PDIF signal and it works on simulator, but create significant jitter, i presume classical PLL topology is better?
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Old 22nd December 2016, 05:53 PM   #8
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Quote:
Originally Posted by alexandar888 View Post
Is it possible to construct preamble detector from logic gates (discrete) ?

I do something similar to oversampling S/PDIF signal and it works on simulator, but create significant jitter, i presume classical PLL topology is better?
Yes, it's possible, but, as I mentioned earlier, I believe most DIR chips utilize the preamble for clock recovery reference, I recall that the Cirrus chips long have. So, no need to custom build this from the gate level.
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Old 22nd December 2016, 05:59 PM   #9
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Actually this is the idea - whole S/PDIF receiver constructed from logic gates. Madness I know.

Last edited by alexandar888; 22nd December 2016 at 06:24 PM.
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Old 22nd December 2016, 11:36 PM   #10
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...Madness I know.
I can't say that I disagree with your self-assessment.
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