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Old 4th January 2017, 10:07 AM   #21
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Lets say that we can build a very low jitters Spidiff output...in terms of less than 10ps (only BNC or coaxial)

Anyone has an idea how will that translate in audio quality on the receiver ?
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Old 4th January 2017, 10:55 AM   #22
DF96 is offline DF96  England
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Random jitter causes noise (and possibly noise modulation). Signal-related jitter causes distortion. Both are very small unless jitter is large. It seems normal for people to want jitter specifications which are much better than can reasonably be achieved (especially for those not experienced in digital design and transmission) and also much smaller than can be heard. A good way to get high jitter is to take a very low jitter clock and just 'glue' it on to existing circuitry, yet this is what many audiophiles do.

Last edited by DF96; 4th January 2017 at 10:55 AM. Reason: typo
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Old 4th January 2017, 11:47 AM   #23
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We are studying to make a Spidif hardware that will be clocked after the IC...using high quality clocks and flipflops....so we are reasonable sure to achive 5-9ps of jitter on the output (coaxial and bnc). Most spidif solutions have 100ps of jitter on the output + optical connector jitter of 1.5ns. I am wondering if anyone thinks its a good idea to build such hardware with above specs
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Old 4th January 2017, 02:06 PM   #24
sesebe is offline sesebe  Romania
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Quote:
Originally Posted by cdsgames View Post
We are studying to make a Spidif hardware that will be clocked after the IC...using high quality clocks and flipflops....so we are reasonable sure to achive 5-9ps of jitter on the output (coaxial and bnc). Most spidif solutions have 100ps of jitter on the output + optical connector jitter of 1.5ns. I am wondering if anyone thinks its a good idea to build such hardware with above specs
And you will evaluate this jiter using yous speakers ?!?
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Old 4th January 2017, 03:48 PM   #25
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Quote:
Originally Posted by cdsgames View Post
We are studying to make a Spidif hardware that will be clocked after the IC...using high quality clocks and flipflops....so we are reasonable sure to achive 5-9ps of jitter on the output (coaxial and bnc). Most spidif solutions have 100ps of jitter on the output + optical connector jitter of 1.5ns. I am wondering if anyone thinks its a good idea to build such hardware with above specs
Hi Ioan,

Wouldn't any jitter be baked into the spdif (by the i2s -->spdif chip (WM8804 or AK4113 etc)) already... you can reclock the new overall spdif clock, but not the i2s encoded within it, can you, isn't it too late?
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Old 4th January 2017, 04:08 PM   #26
TNT is offline TNT  Sweden
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Jitter can never be introduced as long as a signal stays digital. The timing between two samples needs to be known by the decoder. Jitter can be buried into the signal itself and it happens in the ADC stage. Jitter on a s/pdif line is not "introducing" jitter to the signal, it is causing jitter at the point of digital word conversion to analog because the clock used, is extracted from the s/pdif link (nothing has happened to the digital words).

(The above is valid for a standard (old) drive / dac configuration. There are mechanisms to avoid jitter at conversion e.g. buffer/re-cklocking, PLL etc.)

//

Last edited by TNT; 4th January 2017 at 04:12 PM.
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Old 4th January 2017, 04:16 PM   #27
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What re-clocking does is time align or set the signals being relocked to the time domain of the re-clocking signal. Re-clocking doesn't necessarily or inherently reduce jitter on the signals being re-clocked. Instead, jitter on the signals being re-clocked will be substituted for the jitter on the re-clocking signal. The difficulty is that it probably will not be a trivial endeavor to produce a re-clocking signal with less jitter than have the signals being re-clocked. That certainly will be true for a DAC utilizing S/PDIF signal recovery via an PLL based digital input receiver chip without benefit of some closed-loop (between DAC and data source) clock architecture.
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Old 5th January 2017, 01:35 AM   #28
Gusser is offline Gusser  United States
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Originally Posted by TNT View Post
...... A shame that the interface wasn't made with one physical link carrying data downstream and one for the clock sent the other direction. But hey, its a consumer standard and need to be cheap.

//
Some early digital audio interfaces did just that. Sony used such an interface in the mid 1980s on their first generation DVTR.

While not obvious in the audiophile world, there are very good reasons for a single wire* serial AES standard such as broadcast plants. Consider where I work we have an AES matrix switcher that has 2048 inputs by 2432 outputs! Now if there was a separate clock line, that matrix would have to be twice as large. Then consider the timing skew nightmare!

SPDIF is not much unlike AES-1992 which is just a balanced signal at a higher voltage level 7-10vpp. Then there's AES-3 which is very similar to SPDIF except that AES-3 is 1 vpp on 75ohm coax where as SPDIF is 600mv IIRC.

There are also some minor bit stream differences between AES and SPDIF that can basically be ignored these days. They dealt with early copy protection on consumer DAT recorders but were never really implemented in practice.

I have taken AES-3 feeds directly into many consumer AV receivers SPDIF inputs via a simple BNC to RCA adapter for low cost production room monitoring and it works just fine. The receiver just has to support 48khz PCM which most do since DVD has been around.

*A balanced AES switcher still uses a single crosspoint layer. They just unbalance on input and re-balance on output just as with large analog switchers.

Last edited by Gusser; 5th January 2017 at 01:40 AM.
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Old 5th January 2017, 07:50 AM   #29
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No encoding is different that jitter....we can take the encoded signal and realign with bclk (clean) or mclk (clean)

Everything will be done in FPGA with the realignment outside (a la Kali)

Yeah we think that jitter will be closer to 6ps than to 10.


Quote:
Originally Posted by sckramer View Post
Hi Ioan,

Wouldn't any jitter be baked into the spdif (by the i2s -->spdif chip (WM8804 or AK4113 etc)) already... you can reclock the new overall spdif clock, but not the i2s encoded within it, can you, isn't it too late?
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Old 5th January 2017, 09:29 AM   #30
sesebe is offline sesebe  Romania
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How you can measure or detect a so low level of jitter?
Even with expensive equipment it is difficult to make such a measurement ... how can you hear this little jitter?
If you still hear a difference then certainly these differences are caused by something else and not by the jitter.
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