I use such type DiyInHK regulators powering my JLSounds boards.
I have several regulators (and several dual bobbin, two secondary 40VA transformers), so no "wasting" to powering even in the dirty side.
But...in the DiyInHK regulator's primary side -Murata- filter is the weakest point of this layout. After few hours it's about 50C degrees warm (this is the dirty side power). LT3042 chip (on the soldering side) is more than lukewarm, so I glued there little small aluminium heatsink.
40VA transformer is not overestimated, it's about 40C warm after few hour operation.
I have several regulators (and several dual bobbin, two secondary 40VA transformers), so no "wasting" to powering even in the dirty side.
But...in the DiyInHK regulator's primary side -Murata- filter is the weakest point of this layout. After few hours it's about 50C degrees warm (this is the dirty side power). LT3042 chip (on the soldering side) is more than lukewarm, so I glued there little small aluminium heatsink.
40VA transformer is not overestimated, it's about 40C warm after few hour operation.
Hi Soren,
I think there is a real opportunity here, i.e., adding a simple firmware option to use external fixed frequency clock instead of the internal one.
There are quite many members here owning various clocks (NKD, Crystek, Pulsar, etc.) whom I am sure will be wanting to try them with the DAM using something like Ian's FIFO to synchronously drive everything. Together with the improved power supply in the DAM1121 you have a real winner right there.
If such a firmware option exists I for one will immediately buy a DAM1121-01.
Appreciate if you can consider it. If anything I certainly want to see/hear what different clocks sound like.
Thanks.
True. This is because the DAM and the I2S source run their own clocks and the FIFO is to absorb the clock differences as the DAM adapts its clock rate according to the I2S source.
Ian's FIFO/Clock board has clock fanout to drive multiple boards. Thus the ideal setup is to use the clocks there and then drive all other boards using the same clock in a synchronous manner. This way FIFOs are no longer needed.
That would probably be pretty easy, the dam1121 already support an external Si570, checking for its presence, could probably just add an option to bypass the audodetect.... Although I consider the Si570 more than good enough, but people here like to experiment
I'm trying to get a grip on this issue, it's important to me as I'm going to implement at 3-ways system with 3*dam.
Don't we need to see word clock and system clock as two different things?
- it's important that there is very little jitter just befor the DA conversion takes place, this require very good clocks and jitter handling - hence the FIFO
- frequency drift/jitter (words clock drift) between channels, most important in digital x-over seniors.
In my set-up, I will use a nanoDIGI as x-over delivering 3*SPDIF to 3*DAM, I expect no frequency drift/"word jitter" between channels - should I?
Would it be an advantage to use one board clock as system clock master and the two other DAC clocks configured as slaves?
Søren any thoughts?
Don't we need to see word clock and system clock as two different things?
- it's important that there is very little jitter just befor the DA conversion takes place, this require very good clocks and jitter handling - hence the FIFO
- frequency drift/jitter (words clock drift) between channels, most important in digital x-over seniors.
In my set-up, I will use a nanoDIGI as x-over delivering 3*SPDIF to 3*DAM, I expect no frequency drift/"word jitter" between channels - should I?
Would it be an advantage to use one board clock as system clock master and the two other DAC clocks configured as slaves?
Søren any thoughts?
That would probably be pretty easy, the dam1121 already support an external Si570, checking for its presence, could probably just add an option to bypass the audodetect.... Although I consider the Si570 more than good enough, but people here like to experiment
That's great! I look forward to the firmware revision.
You have many options, like using a tube buffer or load custom filters. With a good implementation, like great power supplies and output buffers, it will beat any Schiit.
(at least in mine and some others opinion, Schiit fans might have a different opinion)
Any unit offering a balanced output provides the potential for common mode cancellation on the cable connection to the next unit. This has nothing to do with cancelling internal conversion errors in the DAC.
Yes, one DAM board can use the 2 channels to form one singel channel balanced output and you have the possibility to configure if it is to output R or L.
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Yes, one DAM board can use the 2 channels to form one singel channel balanced output and you have the possibility to configure if it is to output R or L.
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If the errors are the same on + and -. Which they never are.... There can be come advantages with R-2R DACs, but that is because of statistics....
Balanced operation was inverted to cancel noise on cables.
But this have to depend on the device... Certain devices have to distort kind of the same way, if the circuit is 100% the same.. so that means that the device-specific distortions is canceled out.
Also, if there is any power-supply induced distortions, it should be canceled out.
Usually balanced gain stages have less distortion, which have to depend on that exact cause?
Circuit noise should be the less good thing with balanced circuits, since you have twice active devices - which means twice(3dB) as much noise. Not to confuse that with the cable noise cancellation, which is also another plus on balanced circuits.
Good evening all!
First post here. Received my two beautiful 1121 boards today.
Designing a dual mono, master-slave system.
Just want to straighten out some question marks.
1. EN_AUD: (J1-2)
I know this pin is open collector output with internal pull-up when master, input for slave. Should connect from master to slave?
But what is actually the logic (function) of this pin?
2. SPDIF :
SPDIF input only connected to Master. Master transfers via I2S to slave? Input select command ignored by slave?
3. GND Analog vs Digital
Is Analog ground (on J1) separated from Digital ground (on J2, J3) ?
Thanks,
/Björn
First post here. Received my two beautiful 1121 boards today.
Designing a dual mono, master-slave system.
Just want to straighten out some question marks.
1. EN_AUD: (J1-2)
I know this pin is open collector output with internal pull-up when master, input for slave. Should connect from master to slave?
But what is actually the logic (function) of this pin?
2. SPDIF :
SPDIF input only connected to Master. Master transfers via I2S to slave? Input select command ignored by slave?
3. GND Analog vs Digital
Is Analog ground (on J1) separated from Digital ground (on J2, J3) ?
Thanks,
/Björn