I was thinking that if you feed sck to akm...it will create bcl/lrck for i2s master (to be feed to rpi)
I am imagining a akm IC with a clock that has better phase noise (jitter) than a Crystek. All delta sigma need a good clock. Kali is great at 3.80 but on our latest DAC (boss) we measured 700fs of jitter. Next gen clock will be at least 3x less.. (not even talking about jitter but phase noise at important frequencies)
Isn't Kali using the same clocks the Boss is using?
To go to fs levels I would imagine using something like an Si5xx solution..
Its not what you know but who you know.
You could try getting one via a site like 'From Japan';
FROM JAPAN: Japanese auction and shopping proxy service
No ideas about the acko S03 external clock on AK449* ?
In the AKM datasheet you can use registers to adjust internal/external clock.
But I never red about a external clock on AK449*
In the AKM datasheet you can use registers to adjust internal/external clock.
But I never red about a external clock on AK449*
HTML:
Register address: 00 (Control 1) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| Reset chip without initializing registers |_|_|_|_|x|x|x|_| Interface mode: 16bit, 24bit, 32bit, I2S, LJ... (1) |_|_|x|_|_|_|_|_| External digital filter clock: 768KHz/384KHz |_|x|_|_|_|_|_|_| Enable/disable external digital filter mode |x|_|_|_|_|_|_|_| Master Clock frequency Setting: auto/manual (2)(3) NOTES: (1)- The only requirement for bitclock is >= 2x bit depth. Bitclock could be 32fs, 48fs or 64fs. Not limited to always be 64fs as in ESS DACs (2)- Auto: detects master clock frequency and sampling frequency (44.1KHz, 96KHz, ...) automatically; sets oversampling rate (1x, 2x, 4x...) according to input MCKL (this is kind of obvious). Note: AKM calls sample rate "sampling speed" and assigns names to typical sample rates: 44-48KHz="normal", 88-96KHz="double", 175-192KHz="quad"... (3)- Manual: manually set the sampling rate (44.1KHz, 96KHz...) Use reg 01 and reg 05 for sampling rate setting. This means, in its simplest form, manually matching the sampling rate to the incoming data sample rate to use the highest oversampling rate allowed by the system and thus obtain best noise performance. This feature can also be used to select a different sampling rate (typically a lower oversampling rate); for example, if selecting "normal" for 44.1KHz allows 8x oversampling (512fs), selecting "double" results in 4x oversampling (256fs). This allows for experimentation with different oversampling rates and can be used to tailor the sound for those inclined to lower oversampling or even no oversampling. The use of lower oversampling results in higher noise for these kind of DACs. AKM indicates in the datasheet that using a lower oversampling rate (512fs to 256fs) results in a decrease of S/N of 3dB. Register address: 01 (Control 2) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| Mute/unmute |_|_|_|_|_|x|x|_| De-emphasis: Off, 32KHz, 44.1KHz, 48KHz |_|_|_|x|x|_|_|_| Manual setting of sampling speed: "normal", "double"... (1) |_|_|x|_|_|_|_|_| Short Delay/Traditional filter (Minimum/Linear phase) |_|x|_|_|_|_|_|_| Zero data detect mode: Separate channels or ANDed channels |x|_|_|_|_|_|_|_| Zero data detect ON/OFF NOTES: (1)- Manual sampling speed setting uses 3 bits. The third bit is in reg 05. See notes on register 00 for additional info on manual settings Register address: 02 (Control 3) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| Filter cutoff slope: fast/slow |_|_|_|_|_|_|x|_| MONO mode: left/right |_|_|_|_|_|x|_|_| Invert output pin level on zero detect |_|_|_|_|x|_|_|_| MONO/STEREO mode |_|_|_|x|_|_|_|_| DSD Data on clock falling/rising edge |_|x|_|_|_|_|_|_| DSD master clock frequency:512KHz/768KHz |x|_|_|_|_|_|_|_| PCM/DSD mode Register address: 03 (Left Channel Attenuation) 7 6 5 4 3 2 1 0 |x|x|x|x|x|x|x|x| Attenuation (1) NOTES: (1)- 256 levels, 0.5 dB each. 00=mute; ff=max volume Register address: 04 (Right Channel Attenuation) 7 6 5 4 3 2 1 0 |x|x|x|x|x|x|x|x| Attenuation (1) NOTES: (1)- 256 levels, 0.5 dB each. 00= mute; ff= max volume Register address: 05 (Control 4) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| Super Slow filter on/off |_|_|_|_|_|_|x|_| Bit 3 of the manual sampling speed setting (see reg 01) |_|x|_|_|_|_|_|_| Left channel phase invert ON/OFF |x|_|_|_|_|_|_|_| Right channel phase invert ON/OFF Register address: 06 (control 5) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| DSD bit 0 of sampling speed selection (bit 1 is in reg 9)(1) |_|_|_|_|_|_|x|_| DSD Mode: Direct/Convert to PCM (2) |_|_|_|_|x|_|_|_| DSD Automute release when Automute release is in "hold" |_|_|_|x|_|_|_|_| Automute release: Auto/hold (3) |_|_|x|_|_|_|_|_| Right Channel DSD flag when detecting full scale signal |_|x|_|_|_|_|_|_| Left Channel DSD flag when detecting full scale signal |x|_|_|_|_|_|_|_| DSD AutoMute: ON/OFF (4) NOTES: (1)- There is no facility for setting auto sample rate detection for DSD. The use must detect the incoming DSD sample speed and match the sampling speed. Will have to experiment to see what is the effect of sample speed mismatch. (2)- In DSD direct mode, the volume control and delta-sigma modulator are bypassed. In PCM mode, it converts to PCM and uses volume control block and delta-sigma modulator. DSD direct with a combination of the internal filter and simple output filter meets the filter specification of the SACD Scarlet Book. (3)- Automute condition disappears when data becomes under full scale (4)- Automute condition is when data is full scale Register address: 07 (Control 6) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| Synchronize ON/OFF (1) NOTES: (1) Synchronizes multiple DACs when used together in the same system. Read data sheet for more information. Register address: 08 (Control 7) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|x|x| Sound Quality Control Setting (1) NOTES: (1): Sound Control has 3 settings: "1", "2", "3". The AK4495 data sheet shows additional settings "4" and "5". These setting refer to the 5 different filters that are available in the DAC. They serve the same function as the filter selection bits specified in the other registers. What is unclear is which register takes precedence. Register address: 09 (Control 8) 7 6 5 4 3 2 1 0 |_|_|_|_|_|_|_|x| DSD bit 1 of sample speed selection (see also reg 5) |_|_|_|_|_|_|x|_| DSD filter selection when in DSD direct modeI think the PPS 22uF will be better especially in analog section
These polarized capacitors 10uF as suggested for Digital and Analog (3.3v and 5v) may be of greater value to how much?
For example 100uF? It may be of tantalum, or is critical to be electrolytic? Cause instability?
Don't think the LM49723 will be stable in the circuit as drawn. You will definitely need to remove the 1n capacitor in the feedback loop and even then it will probably not be stable because of the 22n capacitor. There are also issues with the value of the Rf resistance. Avoid!
I think the best op amp for that circuit is AD4898-1.
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Do you mean connect the Turbo MCK to the (the doctor...) PIN 46 on the AK4490 DAC ?
yes trivial... Sorry for my question
thank's
The figure 40 page 62 circuit is certainly the simplest for unbalanced out ( Don't know about the best but I like simple minimum component solutions). I really like the sound of the AD4898 op amp which is also available as a dual so you could do both channels with one op amp. Low noise, high output current, one of the best op amps for buffer/LPF applications. All imho and ymmv.
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