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S/PDIF to multible WM8804
S/PDIF to multible WM8804
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Old 11th December 2015, 01:05 PM   #1
ralfnap is offline ralfnap  Germany
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Join Date: Oct 2014
Default S/PDIF to multible WM8804

i am building several DACs with S/PDIF input. I am running 8 PCM1794 in parallel. I convert S/PDIF with WM8804 to i2s. Then feeding all DACs with i2s signals. The problem is noise and reflections.
Now I plan to feed each DAC with one WM8804. Instead of the 4 i2s signals to each DAC, I have one S/PDIF signal to 8 WM8804. Is it possible to feed 8 WM8804 with just one S/PDIF signal without any buffer?
(Feeding 8 PCM1794 with one i2s signal from one WM8804 works. The reflection and noise problems could be solved but I think the new concept is a better solution)


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Old 11th December 2015, 07:24 PM   #2
twest820 is offline twest820
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Join Date: Jun 2009
The two arrangements are equivalent. To see whether it helps any just change whatever impedance you're using in I2S signal integrity analysis to the 75 ohms of SPDIF. If that can't be done due to lack of a layout model it's best to address that first rather than attempting to design by guesswork.
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Old 11th December 2015, 09:12 PM   #3
Tam Lin is offline Tam Lin
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Join Date: May 2010
I think it more prudent to solve the noise/reflection problem with the addition of terminating resistors or a clock driver.
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Old 14th December 2015, 08:44 AM   #4
ralfnap is offline ralfnap  Germany
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Join Date: Oct 2014
Thank you!
The reflection problem was solved with additional resistors.
But why not using 8 WM8804 in parallel? Are there any problems using one S/PDIF signal for WM8804 receivers?
My DAC had very big improvements with 8 PCM1794 in parallel. (SQRT(n) rule!)
Extra benefit are the very short i2s connections between WM8804 and PCM1794 and the possibility to use even one WM8804/PCM1794 module stand alone.
My DAC is working in OS-mode WITH digital filtering. So I must use MCLK signal, too. I do not want to spread 2-6 MHz BCLK and 12 MHz MCLK around the hole system.
With my actual DAC and proper termination I can reach 10 mV of HF noise at the output. This is not bad but maybe could be improved by the other solution.
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Old 23rd May 2016, 04:07 PM   #5
ralfnap is offline ralfnap  Germany
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Join Date: Oct 2014
Splitting one SPDIF signal to multiple receivers is easy. Just the termination resitor has to be changed. 1:4 R47 (45) 1:8 R56 (58.3)
Works without buffer! The quality i2s (jitter) improves by SQRT(8)!
Best solution: 4 PCM1794 each driven by one WM8804. 2 PCM/WM8804 on one board with one tent clock.
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