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Old 11th November 2014, 07:29 AM   #1
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Default FPGA based FIR filter design

Hi, my name is Rinalds, I am from Latvia!


I have an idea. I want to create device with FPGA based 1D FIR filter that
  1. supports sampling frequencies up to 96kHz (should it support larger sampling frequencies?);
  2. device has 4 FIR filters, each has 8192 long impulse response they can be configured to function as two separated FIR filters (each with 16384-long impulse response) or as 4 separated FIR filters (each with 8192-long impulse response) it depends on user configuration;
  3. one I2S input, but two I2S outputs (second I2S is active if 4 separated FIR filters are chosen);
  4. capability to reload impulse response from PC. I want to design software what could accept coefficients from SPL meter and convert these values to impulse response;
  5. capability to connect more than one device. For example, if You want to create active crossover for 2 speakers, You can take two devices and use each device only for one channel;
  6. device dimensions no larger than 5cm by 10cm (~2" by ~4");
  7. user only needs to provide clean I2S input source, power supply and USB connectivity to change impulse response.

I have more features, but i wanted to know if someone is interested in such product, if so what features You wanted to be included?


At this moment I have first working prototype for described diagram below.


fpga_block_diagram.jpg



Maximum input data width is 24bits and 16 bits is for impulse response coefficients. Filtering is done on full precision. At the end of filtering data width is chosen depending on what DAC You are using, for example for test purposes I have PCM1795 and it accepts 32 bits, so I left 32 bit precision.



I want to hear comments or suggestions from You!

Best regards,
Rinalds Ruskuls
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