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Very sad news.
Another great one - gone. May he rest in peace, where ever he may be.
Yes, a very sad day...
I am still interested about a pointer(s) about the thesis explained and the given figures & related measurements...
Hp
Building instructions are very simple:
- polarized capacitors, pay attention to the polarity
- Led, pay attention to the polarity
- Mini-Circuits RF transformers, pay attention to place correctly pin 1 (dot)
- and above all be careful not to interchange capacitors and inductors because they do not have a label that identifies them once installed
You can refer to the board picture I have published.
I can provide support, but my first question will be about the above indications.
I can check with a picture the polarized capacitors and the RF transformers. To check the polarity of the SMD Led you will remove them.
And there is no way to check the value of SMD capacitors and inductors unless you remove all of them and check one by one with a reliable LC meter (not very simple measuring a few pF 0805 SMD capacitor).
At the end you should remove, throw out and replace all of them.
Yes, but you should use a fanout buffer like the NB3L553 if you are planning to distribute the clock after the sine to square converter.
Otherwise you can distribute the sine wave output of the oscillator using a power splitter. Then you need a sine to square converter for each digital input.
Otherwise you can distribute the sine wave output of the oscillator using a power splitter. Then you need a sine to square converter for each digital input.
You can use something like this from Mini-Circuits
Z99SC-62-S+
2 Ways Power Splitter, 0.5 - 600 MHz, 50Ω
Connector Type: SMA
Z99SC-62-S+
Z99SC-62-S+
2 Ways Power Splitter, 0.5 - 600 MHz, 50Ω
Connector Type: SMA
Z99SC-62-S+
Your 2 last posts information would be spiffing to have in the more general document you just posted. Also the info about the signal level out of the multipliers. Actually, looking at these bunch of pdf's again, I could not find a chart with signal interface specs; in/out impedance, signal level and shape, connector type. This info would make this timing Lego game easier ;-)
Columns and rows are very effective in order to get a complete view and consistent content.
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Columns and rows are very effective in order to get a complete view and consistent content.
//
I believe that the questions about clock distribution are not strictly related to these devices, they are general RF and digital communication matters.
If you get a Crystek oscillator you have the same situation when ditributing the clock.
Anyway I will add the infos to the guide.
About the multiplier, the informations you are looking for are at page 5 of the second part of the guide:
It's a frequency multiplier that duplicate the input frequency. It's a state of the art device because the phase noise added for each duplication is exactly 6dB (even less very close to the carrier) as expected from the theory.
It can be used with base oscillators from 5.6448 MHz up to 24.576 MHz to get the output up to 98.304 MHz.
The output of this frequency doubler is sine wave therefore it needs a sine to square converter to be connected to digital devices such as FIFO or DAC (for example the TWTMC-STS).
Base Oscillator type: any
Base Oscillator Frequencies: 5.6448 MHz, 6.144 MHz, 11.2896 MHz, 12.288 MHz, 22.5792 MHz, 24.576 MHz
Output: 50 Ohm sine wave (+10 dBm to +15 dBm)
Output Frequencies: base oscillator frequency x 2 or x 4 (series of 2) up to 98.304 MHz
Board size: 99mm x 75mm (excluding SMA connectors)
Power supply: 12-24 Vdc 30 mA
Suitable box: Hammond 1455J1201 (Mouser part 546-1455J1201)
Board options: finished and semi-finished
Note: max 2 doublers in series, supplied without box
If you get a Crystek oscillator you have the same situation when ditributing the clock.
Anyway I will add the infos to the guide.
About the multiplier, the informations you are looking for are at page 5 of the second part of the guide:
It's a frequency multiplier that duplicate the input frequency. It's a state of the art device because the phase noise added for each duplication is exactly 6dB (even less very close to the carrier) as expected from the theory.
It can be used with base oscillators from 5.6448 MHz up to 24.576 MHz to get the output up to 98.304 MHz.
The output of this frequency doubler is sine wave therefore it needs a sine to square converter to be connected to digital devices such as FIFO or DAC (for example the TWTMC-STS).
Base Oscillator type: any
Base Oscillator Frequencies: 5.6448 MHz, 6.144 MHz, 11.2896 MHz, 12.288 MHz, 22.5792 MHz, 24.576 MHz
Output: 50 Ohm sine wave (+10 dBm to +15 dBm)
Output Frequencies: base oscillator frequency x 2 or x 4 (series of 2) up to 98.304 MHz
Board size: 99mm x 75mm (excluding SMA connectors)
Power supply: 12-24 Vdc 30 mA
Suitable box: Hammond 1455J1201 (Mouser part 546-1455J1201)
Board options: finished and semi-finished
Note: max 2 doublers in series, supplied without box
What about a dual clock connection like this?
A vastly used clock scheme for DACs.
Connected like this, one oscillator shut down at a time, there would be only one frequency doubler(s)/ squarer chain necessary.
Is there anything to be said against this, like maybe a long startup time to stabilize the oscillator circuit, so that both should be running uninterrupted?
A vastly used clock scheme for DACs.
Connected like this, one oscillator shut down at a time, there would be only one frequency doubler(s)/ squarer chain necessary.
Is there anything to be said against this, like maybe a long startup time to stabilize the oscillator circuit, so that both should be running uninterrupted?
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Our oscillators don't have a enable pin, so this configuration is not possible.
Moreove you cannot use the same frequency doubler for different frequencies, each needs its own multiplier because the inside filters are different from a frequency to another.
Oh, yes, thanks Andrea.
I overlooked the specific doubler fact.
But is it possible to tie them together after the squarers, resp. shut one of the squarers down or do I have to reposition each time the oscillator for the specific sampling frequency?
Or ist there another way (over buffers) that you suggest, to bring them together?
I overlooked the specific doubler fact.
But is it possible to tie them together after the squarers, resp. shut one of the squarers down or do I have to reposition each time the oscillator for the specific sampling frequency?
Or ist there another way (over buffers) that you suggest, to bring them together?
I probably shouldn't get into this subject, but if anyone is actually thinking of using a clock buffer of their own design and layout then they should probably take care how the device is powered and bypassed. Textbook solutions may or may not give best audible performance.
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I will also probably need enabling/disabling functionality in my application. First I thought to implement this by using the enable signal to switch a relay and simply cut off the output. But now I'm thinking to maybe use the LTC6957 buffer. If I read the datasheet right, you could feed it sine wave and use it as squarer, and also do distribution into 2 signals, and finally it has enable functionality for both square outputs. I'm no clock expert so if I overlook something here then tell me...
Sorry, but I don't understand what you have to connect after the squarer, can you elaborate?
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